TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 25

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.1.3
Internal RAM0
Internal RAM2
8kB (Remap)
Multilayer AHB
Interrupt Controller
NANDF Controller
16kB
The TMP901CM uses a multilayer AHB bus system with 7 layers.
Synchronous
LCD Data Process
Serial Port
Multi Layer Bus Matrix0
(Bus Master3)
(Bus Master4)
I2S I/F
(2ch)
(1ch)
Accelerator
(1ch)
Controller
Data Cache
LCD
16Kbyte
CPU Inst.
CPU Data.
DMA1
DMA2
Internal RAM1
USB Host 1.1
CPU Data
Boot ROM
Controller
LCDDA
LCDC
16kB
USB
8kB
LCDDA
CPU Inst.
LCDC
CPU Data
ARM926EJ-S
DMA1
DMA2
TMPA901CM- 24
(Bus Master1&2)
Bus Interface
CPU Data.
CPU Data
DMA1
DMA2
TM
Controller
USB
SDR SDRAMC
Memory
SRAM
NORF
Bus Matrix3
Multi Layer
External Bus Interface
Controller
Instruction Cache
USB Device 2.0
DMA Controller
(Bus Master5&6)
16Kbyte
General purpose I/O
System Controller
Watch Dog Timer
Touch Screen I/F
Power Management
External Interruption
16Timer/PWM (6ch)
A/D converter (4ch)
PLL Clock Gear
Key board matrix
I2C I/F (1ch)
RTC/Melody
UART (2ch)
(Bus Master7)
OFD
Controller
DDR SDRAMC
Memory
NORF
SRAM
Bus Matrix2
Multi Layer
TMPA901CM
2010-07-29