TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 785

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Read/Write
(HCD)
Read/Write
(HC)
Read/Write
(HCD)
Read/Write
(HC)
bit Symbol
Reset state
bit Symbol
Reset state
[31]
[30]
[29:7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
5.
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus
register and the corresponding bit in the HcInterruptEnable register is set and the
MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus.
in this register leaves the corresponding bit unchanged. On read, the current value of this
register is returned.
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
Writing a 1 to a bit in this register sets the corresponding bit, whereas writing a 0 to a bit
HcInterruptEnable Register
Mnemonic
MIE
OC
RHSC
FNO
UE
RD
SF
WDH
SO
MIE
31
15
0
R/W
R
OC
30
14
0
MasterInterrupt
Enable
Ownership
Change
Reserved
RootHubStatus
Change
FrameNumber
Overflow
Unrecoverable
Error
ResumeDetected
StartofFrame
WritebackDone
Head
Scheduling
Overrun
29
13
Field name
28
12
Reserved
27
11
TMPA901CM- 784
26
10
A '0' written to this field is ignored by the HC. A '1' written to this field
disables interrupt generation due to events specified in the other bits of
this register. This is used by HCD as a Master Interrupt Enable.
0: Ignored
1: Disables interrupt generation due to Ownership Change.
0: Ignored
1: Enables interrupt generation due to Root Hub Status Change.
0: Ignored
1: Enables interrupt generation due to Frame Number Overflow.
0: Ignored
1: Enables interrupt generation due to Unrecoverable Error.
0: Ignored
1: Enables interrupt generation due to Resume Detect.
0: Ignored
1: Enables interrupt generation due to Start of Frame.
0: Ignored
1: Enables interrupt generation due to HcDoneHead Writeback.
0: Ignored
1: Enables interrupt generation due to Scheduling Overrun.
25
9
24
8
23
Reserved
7
RHSC
22
6
0
Address
Function
FNO
21
5
0
20
UE
4
0
(0xF450_0000) + (0x0010)
R/W
19
RD
3
R
0
18
SF
2
0
TMPA901CM
2010-07-29
WDH
17
1
0
SO
16
0
0