TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 35

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Exit 1-IR
Pause-IR
Exit 2-IR
Update-IR
This is a temporary controller state.
When the TAP controller is in this state, it moves to either the Pause-IR state if TMS is
held low, or the Update-IR state if TMS is held high.
This state allows the shifting of the instruction register to be temporarily suspended.
Both the instruction register and the data register retain their current states.
When the TAP controller is in this state, it remains in the Pause-IR state if TMS is held
low, or moves to the Exit 2-IR state if TMS is held high.
This is a temporary controller state.
When the TAP controller is in this state, it moves to either the Shift-IR state if TMS is
held low, or the Update-IR state if TMS is held high.
This state allows the instruction previously shifted into the instruction register to be
output in parallel on the rising edge of TCK. Then it becomes the current instruction,
setting a new operational mode.
When the TAP controller is in this state, it moves to either the Run-Test/Idle state if
TMS is low, or the Select-DR-Scan state if TMS is high.
TMPA901CM- 34
TMPA901CM
2010-07-29