TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 702

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

10. RTCALMINTCTR (RTC ALM Interrupt Control Register)
[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[Description]
Bit
a. <ALMINTCLR >
b. <RTCINTCLR>
c.
d. <AINTEN2>
e. <AINTEN64>
f.
g. <AINTEN8192>
h. <RTCINTEN>
Clears the enabled alarm interrupt flag.
Clears the enabled RTC interrupt flag.
Enables or disables the alarm (1 Hz) interrupt.
Enables or disables the alarm (2 Hz) interrupt.
Enables or disables the alarm (64 Hz) interrupt.
Enables or disables the alarm (512 Hz) interrupt.
Enables or disables the alarm (8192 Hz) interrupt.
Enables or disables the RTC interrupt.
<AINTEN1>
<AINTEN512>
ALMINTCLR
RTCINTCLR
AINTEN1
AINTEN2
AINTEN64
AINTEN512
AINTEN8192
RTCINTEN
Symbol
Bit
WO
WO
R/W
R/W
R/W
R/W
R/W
R/W
Type
TMPA901CM- 701
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Reset
Value
Alarm interrupt flag clear
0y0: Invalid
0y1: Clear
RTC interrupt flag clear
0y0: Invalid
0y1: Clear
Alarm (1 Hz) interrupt enable
0y0: Disable
0y1: Enable
Alarm (2 Hz) interrupt enable
0y0: Disable
0y1: Enable
Alarm (64 Hz) interrupt enable
0y0: Disable
0y1: Enable
Alarm (512 Hz) interrupt enable
0y0: Disable
0y1: Enable
Alarm (8192 Hz) interrupt enable
0y0: Disable
0y1: Enable
RTC interrupt enable
0y0: Disable
0y1: Enable
Address
Read as undefined. Write as zero.
(0xF003_0000) + (0x0200)
Description
TMPA901CM
2010-07-29