MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 15

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

distributed system. It contains both protocol generators and
physical interfaces, to allow an MCU to communicate with
devices on the bus using two different SPI interfaces. Four
differential buses are provided. The physical layer uses a
two-wire bus to carry power and signal. The physical layer
uses wave-shaped voltage signals for commands from the
master and wave-shaped current signals for responses from
the slaves. The protocol and physical layer conform to the
DSI 2.02 specification.
connected between the two bus wires and capacitors
between the bus wires and ground. Because the voltage
change on either of the bus wires to ground is only 1/2 the
Table 5. High Side and Low Side Typical Voltages (Voltage Relative to Ground)
RESET (RST)
known state as indicated in the section entitled
and Bit Descriptions on page
CHIP SELECT n (CSn)
ground. When high, the associated SPIn port signals are
ignored. The SPIn transaction is signaled as completed when
this signal returns high.
MASTER OUT/SLAVE IN 0 (MOSI0)
sampled on the positive (rising) edge of SCLK0. There is no
MOSI pin or function for SPI1.
SERIAL CLOCK (SCLKn)
controls the clocking of data to SPIn and data reads from the
SPIn.
MASTER IN/SLAVE OUT (MISOn)
changes on the negative (falling) transition of the associated
SCLKn.
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
16.
The 33781 is intended to be used as a master device in a
The equivalent bus capacitance consists of capacitors
When pulled low, this will reset all internal registers to a
This input is used to select the SPIn port when pulled to
This is the SPI data input to the device. This data is
This is the clock signal from the SPIn master device. It
This is the SPIn data from SPIn to the SPIn master. Data
V
IDLE
MID
0
= V
SUPn
/2.
Vmid-2.25
Low Side
HIGH
29.
(16)
FUNCTIONAL DESCRIPTIONS
Vmid-0.75
FUNCTIONAL PIN DESCRIPTIONS
LOW
SPI0 Register
(16)
INTRODUCTION
V
IDLE
SUPn
amount of change between the two bus wires, the
capacitance to ground only conducts half as much current as
it would if connected directly across the bus. The equivalent
bus capacitance of a capacitor to ground from the bus wires
is one half of the actual amount of the capacitor. The amount
of capacitance from either bus wire to ground should be kept
the same in order to achieve the lowest radiated EMI energy.
The 2.2nF capacitors required between the bus wires and
ground result in an equivalent of 1.1nF of capacitance across
the bus as seen by either bus wire.
(LS) is the bus wire that is the most negative and high side
(HS) is the bus wire that is the most positive.
the bus waveforms in normal operation.
CLOCK (CLK)
be 4.0MHz.
GROUND (GND)
DIGITAL GROUND (VSS)
DIGITAL GROUND AND IDDQ (VSS_IDDQ)
ANALOG GROUND (AGND)
POWER SOURCE (VCC)
DIGITAL REGULATOR OUTPUT (VDD)
bypassed with a small capacitor to ground (100nF)
Table 5
This is the main clock source for the internal logic. It must
Ground source for DSI/DBUS return.
Ground source for logic.
Used for IDDQ testing during IC manufacturing test.
Ground source for analog circuits.
Nominal +5.0V Regulated Input.
Nominal +2.5V internal regulator Pin. This must be
shows the voltages used for operation. Low side
Vmid+2.25
High Side
HIGH
(16)
FUNCTIONAL DESCRIPTIONS
Vmid+0.75
INTRODUCTION
Figure 5
LOW
(16)
shows
33781
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