MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 24

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI1 COMMUNICATIONS
and are asynchronous to SPI0. There is no MOSI pin or
function associated with SPI1, since there are no commands
sent.
transfer, and
each SPI1 transaction.
CS1 asserts and ends once CS1 negates. The start of an SPI
transaction is signaled by
logic sees more than 16 SCLK1 pulses while CS1 is
asserted, zeros are returned for all additional bits (bits
beyond bit 15). If a SPI1 transaction contains less than 16-
bits (too few SCLK cycles), the data that was in process of
being sent during the transaction is discarded and not saved
for retry.
cyclic fashion. Four of these registers are associated with bus
channel 2, and four are associated with bus channel 3. Data
is deposited into these registers under the following
conditions:
words, the SPI1 state machine monitors outgoing bus
addresses and commands on the channel. If the command
sent is $2 (Request AN0), the address portion of the
command is saved. The response received on the next
command is stored into one of the four 16-bit register pointed
to by the channel 2 cyclic buffer write pointer, along with the
address that generated that response (saved from the
previous transaction) with the bits “01”, completing the 16 bit
24
33781
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
All SPI1 transactions are read only, are 16-bits in length,
SPI1 transfers start with the 1st SCLK1 transition after
There are eight registers which can be read by SPI1 in a
When the bus channel 2 is set for enhanced 10-bit short
Figure 18
Second RX Byte
Second TX Byte
Fourth RX Byte
Fourth TX Byte
Third RX Byte
Figure 17. SPI0 Communications, 32-Bit Burst Transfer Enhanced Short Word DBUS Bit Definitions
Third TX Byte
First TX Byte
First RX Byte
Figure 19
shows the signals associated with an SPI1
contains the order of bits sent for
CS1
CSB
SLCK
MISO
Bit 7
R/W
Bit 7
SA3
being asserted low. If the SPI1
D7
D7
ER
X
X
0
b00 b01 b02 b03 b04 b05 b06 b07 b08 b09 b10 b11 b12 b13 b14 b15
Figure 18. SPI1 16-Bit Burst Transfer Example
ADDR6
SA2
Bit6
Bit6
D6
D6
TE
X
X
0
ADDR5
SDS
SA1
BIt5
BIt5
D5
D5
X
X
0
ADDR4
RNE
SA0
Bit4
Bit4
D4
D4
X
X
write. These last two bits indicate that the transaction
occurred on channel 2. The data bits will only be written if the
status bits for that bus transaction all indicate no errors. If a
status error is indicated, the address and channel indicator
bits are stored as described, but the data bits are all set to
zeros. If there was a bus driver shutdown during the
transaction, no buffer write will occur. Further transactions
are written to the next cyclic buffer register in the same way,
overwriting data if necessary.
transactions, except that the channel indicator bits are “10”,
and writes occur to a separate set of four 16-bit cyclic
registers.
sequence is used except the buffer write occurs only if the
data is all ones or all zeros, and the saved address from the
previous transaction is the complement of the data. The
channel indicator bits are written the same as if the channel
were in normal mode. The buffer pointer always advances,
even if the buffer is not written, so that it is synchronous with
the SPI0 RX buffer pointer.
channel abort.
accomplished in a cyclic buffer way, except the two channels
are concatenated, with channel 3 following channel 2 in the
cyclic sequence. During these buffer reads, if a buffer
position does not contain data, it is skipped. After each buffer
location is read it is cleared by the SPI1 logic.
0
This same sequence occurs for channel three
If the channel has been put into loop mode, the same
The channel buffers are not cleared, in the case of a
Reads from this register by the SPI1 master are also
ADDR3
Bit3
Bit3
ICL
D3
D3
X
X
0
0
ADDR2
Bit2
Bit2
Analog Integrated Circuit Device Data
D2
D2
X
X
0
0
0
ADDR1
FIX0
Bit1
Bit1
Freescale Semiconductor
D9
D1
D9
D1
X
0
ADDR0
FIX1
Bit0
Bit0
D8
D0
D8
D0
X
0