MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 22

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI0 COMMUNICATIONS
start with a command byte and can be followed by 1 or 3
bytes of data. The start of an SPI transaction is signaled by
CS0
byte signals a read or write (write = 1) of data. The last seven
bits (bits 6–0) of the command set a pointer to the desired
register. The 33781 uses 16-bit commands to access control
registers, and 32-bit commands to access both control
registers, and to queue up transfers over the DBUS.
Figure 13
diagram of 32-bit transfers. In these multi-byte transfers, as
long as
the SPI will be a read/write of data to the sequential next
register.
for sending commands and responses over the DBUS. There
are separate command and response registers, and a
transmit queue is used to allow up to 4 bus commands to be
scheduled for each bus. The transmit queue schedules
transfer, and if the transfer will be to/from the addressable
FIFOs, whether the DBUS for that channel is set for Long
Words or Enhanced Short words.
22
33781
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
All SPI0 transactions are either 16 or 32-bits long. They
33781 utilizes, transmit, and receive addressable FIFOs
The bit definitions for SPI0 depend on the type of SPI
being asserted low. The first bit sent (bit 7) of the first
CS0
is a diagram of 16-bit transfers and
is asserted low, each additional byte sent over
SCLK
MOSI
MISO
CS0
WRITE COMMAND
POINT TO D0R0H
00000000
MOSI
MISO
CS0
SCLK
FUNCTIONAL DEVICE OPERATION
Figure 13. SPI016-Bit Burst Transfer Example.
Figure 14. SPI0 32-Bit Burst Transfer Example
LOGIC COMMANDS AND REGISTERS
Figure 14
POINT TO REGISTER
DATA FROM D0R0H
WRITE COMMAND
DATA TO D0R0H
00000000
is a
commands as a circular buffer, accessing the appropriate
command register for the command and data to be sent as
the bus becomes available. Data received in response to the
commands is queued up for sequential response back to the
MCU during the next set of SPI commands. If an SPI0
attempts to write to a transmit register that is not empty the
new command will be ignored.
the first byte of the SPI transaction, the first MOSI bit is 1
(write), and the last seven are the address of the register to
be accessed. During this command byte, MISO returns
dummy bits set to all zeros. During the next SPI transactions,
MOSI updates the data in the register pointed to in the
previous byte with new data, while reading back the old data
via MISO.
framing errors. A framing error is defined as any number of
clocks received that is not either 16 or 32. If that occurs, all
bits sent by the SPI master are discarded and no registers
are update.
transfers. In this transfer the first byte contains the address of
the control register to be written to or read from, and the
second byte is the data to be written. The SPI0 response is
the data from that register, latched at the falling edge of CS0.
If the address pointed to by the first byte is not a control
DATA FROM D0R0L
Figure 14
During an SPI0 transaction the 33781 checks for SPI
Figure 13
DATA TO D0R0L
DATA FROM
REGISTER
REGISTER
DATA TO
shows an example of a write operation. During
shows the bit encoding for 16-bit SPI0 burst
Analog Integrated Circuit Device Data
DATA FROM D0R0STAT
XXXXXXXX
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