MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 36

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWLEN[3:0]–Short Word Length in Bits
command that will be sent onto the specified DBUS channel.
The reset value for these bits is 1000 (8 bits), which is the
default DSI value. Allowed SWLEN[3:0] values range from
8 bits to 15 bits. If an attempt is made to write a value that is
less than 8 bits, a 1 is automatically written to SWLEN3,
thereby making the register value greater than or equal to 8
bits.
CRCLEN[3:0]–CRC Length in Bits
with commands and read back in. The length is valid for both
short and long word commands. The reset value for these
bits is 0100 (4 bits), which is the default DSI value. Allowed
DEV[2:0]–Spread Spectrum Frequency Deviation for
Channel n
spectrum signalling.
which are randomly added to the base time period to achieve
the spread spectrum effect. So for example, if you choose
DEV=011, the bit time will randomly vary from the base time
DnFSEL[7:0] - Channel Frequency Selection Bits
determine the minimum bit time (maximum bit frequency for
a channel. The equation for the minimum bit time is:
FSEL[7:0] bits
36
33781
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
These bits specify the bit length of the short word
These bits specify the bit length of CRCs that are sent out
These bits control the frequency deviation of the spread
DEV[2:0] = 000 - No Deviation.
DEV[2:0] = 001 - 16 1/64 MHz periods Max Deviation
DEV[2:0] = 010 - 32 1/64 MHz periods Max Deviation
DEV[2:0] = 011 - 64 1/64 MHz periods Max Deviation
DEV[2:0] = 100 - 78 1/64 MHz periods Max Deviation
The deviation is the max number of 1/64MHz time periods
These bits select the channel base time period. These bits
((1/16*f
The hex value for x in the equation is represented by the
SPI Data Bit
Read/Write
Reset
SPI Data Bit
Read/Write
Reset
CLK
) x (320 +2x)) where x = 0 to 255 (decimal)
FSEL7
Bit 7
Bit 7
Figure 33. Dn Spread Spectrum Control Register Bit Assignment
0
0
-
Figure 34. Dn Frequency Selection Register Bit Assignments
FSEL6
6
0
6
0
-
FSEL5
5
0
5
1
-
FSEL4
4
0
4
0
-
CRCLEN[3:0] values range from 0 bits (no CRC) to 8 bits. If
an attempt is made to write a value that is greater than 8 bits,
the value 8 (1000) is automatically written into this register.
The CRCLEN[3:0] value overrides the CRCPOLY and
CRCSEED bit values that are beyond what the CRCLEN[3:0]
specifies.
DnSSCTRL REGISTERS
spectrum circuits.
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to this
register. The bit assignments are shown in
period to the base time period plus 1 μ sec in 64 equal steps.
The mode with deviation disabled may be used to achieve
fine control of the bit rate without frequency spreading.
DnFSEL REGISTERS
base time period. There are four of these registers, one for
each DBUS channel. The bit assignments are shown in
Figure
activity on the bus. Any bit changes will take place on the next
DBUS transaction following the conclusion of the SPI write to
the register. Refer to the Spread Spectrum section for more
detail.
rate is 200kbps.
rate and minimum bit time for f
MASKID REGISTER
silicon. This ID can reflect the version, design change
number, or other encoded information. The purpose is for the
central module CPU to be able to know what version of silicon
These registers control the operation of the spread
A write to the register will abort any current activity on the
These read/write registers control the spread spectrum
A write to one of these registers will abort any current
With a 4MHz clock and these bits set to zero the max bit
This read-only register contains seven mask ID bits for the
34.
FSEL3
3
0
3
1
-
Table 8
FSEL2
DEV2
2
0
2
0
Analog Integrated Circuit Device Data
gives some examples of the max bit
CLK
FSEL1
DEV1
1
0
1
0
= 4.0MHz.
Freescale Semiconductor
Figure
FSEL0
DEV0
0
0
0
0
33.