MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 17

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

interface. It handles the digital and physical layer portions of
a DBUS master node. Four separate DBUS channels are
included. The physical layer uses a two-wire bus with analog
wave-shaped voltage and current signals. Refer to
• SPI0 interface and registers to a main MCU
• SPI1 interface and registers to a second MCU
• Four channels of DSI 2.02 protocol state logic
• CRC block for each channel
• Control and status registers
• Four addressable register sets per channel for queuing up
• Pseudo Bus Switch from D0H/L to DPH/L
SPI0 AND REGISTERS
and response registers that are written to and read from the
SPI interface.
Out-Slave-In) is an input and MISO0 (Master-In-Slave-Out) is
an output.
Analog Integrated Circuit Device Data
Freescale Semiconductor
The 33781 is controlled by an MCU through the SPI0
Major subsystems include the following:
to four commands and data per bus. The addressable
buffer acts as a circular buffer for command writes and
data reads.
This block contains the SPI0 interface logic and the control
The IC is an SPI slave-type device, so MOSI0 (Master-
CS0
and SCLK0 are also inputs.
MC33781 - Functional Block Diagram
Clock Generation and Frequency Spreading
Supply Voltage
SPI0 Registers and State Machine
SPI1 Registers and State Machine
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
CRC Generation and Checking
Over-temperature Sensing
HCAP Charging Circuitry
VSUP Voltage Monitor
Logic and Control
Over-current Sensing
Supply Voltage
Figure 10. Block Illustration
Figure
1.
Logic and Control
addresses 87 registers. The organization of the registers is
described in the section entitled
Descriptions on page
SPI1 AND REGISTERS
valid response data from Bus Channel 2 and 3, along with the
slave address, to be read independently by a second MCU.
This block contains the SPI1 interface logic and the response
registers that are read from the SPI1 interface.
Slave-Out) is an output, and
does not use the MOSI (Master-Out-Slave-In) pin or function
as it does not receive commands.
eight registers which are read only.
PROTOCOL ENGINE
registers into the DBUS sequences, and converts DBUS
response sequences to data in the registers.
with a duty cycle determined by the logic state. The protocol
includes Cyclical Redundancy Check (CRC) generation and
validation.
The SPI0 port can handle 2-byte and 4-byte transfers. It
The 33781 has a second SPI port (called SPI1) that allows
The IC is an SPI slave-type device, so MISO1 (Master-In-
The SPI1 port handles only 16-bit transfers. It addresses
This block converts the data to be transmitted from the
The DBUS transmit protocol uses a return to 1 type data
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Power Stage
DBUS Drivers
and Receivers
Pseudo-bus
29.
Switches
Power Stage
CS1
FUNCTIONAL DESCRIPTIONS
SPI0 Register and Bit
and SCLK1 are inputs. SPI1
33781
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