MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 25

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DO[0:9]- Data Bits
the transaction had any CRC or SDS errors (See page
and page 33), then these bits are set to all zeros.
A[0:3] - Sensor Address Bits
of the address sent out during the previous bus transaction.
(DSIF), a data signal (DSIS), and a data return (DSIR) signal.
These are signals internal to the IC associated with the
protocol engine.
which marks the start of a frame. There is a one bit-time delay
before the MSB of data appears on DSIS. Data bits start with
a falling edge on DSIS. The low time is 1/3 of the bit time for
a 1, and 2/3 of a bit time for a 0. Data is transmitted on DSIS
and received on DSIR simultaneously. Receive data is the
captured level on DSIR at the end of each bit time. As a
message is received, it is stored bit-by-bit into the appropriate
receive register. For each data value received, there is a one-
bit status flag (ER) to indicate whether or not there was a
CRC error while receiving the data. At the end of the bit time
for the last CRC bit, DSIF returns to a logic high (Idle level).
A minimum delay is imposed between successive frames as
determined by the DnCTRL register.
from the MCU) to the high and low byte of the data registers
(DnRnH/L). Transactions are scheduled once the CS0 for
that transfer rises. When 9- to 16-bit messages are to be
sent, the user writes to the DnH register first, and then the
DnL register, before the combined 9 to 16-bit data value
DnH:DnL is sent on the DBUS. The user should first check
the TE status flag to be sure the command register is not full
before writing a new data value to DnH and/or DnL. When the
minimum inter-frame delay has been satisfied, and CS0 has
risen, and if no SPI0 framing error has occurred, DSIF will go
low, indicating the start of a new transfer frame.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Data Bit
.
The received data bits from the bus channel transaction. If
The address of the slave that sent the data. This is a copy
DBUS Driver/Receiver communications involve a frame
A message starts with a falling edge on the DSIF signal,
Users initiate a message by writing (via the SPI0 interface
Read
Only
SPI
Bit 0
DO0
Bit 1
DO1
Bit n
Bit 2
DO2
Bit 3
DO3
…………………
Figure 20. DBUS Communications Message
DO4
Bit 4
Figure 19. SPI1 Bit Encoding
Bit 5
DO5
32
DO6
Bit 6
Bit 7
DO7
C[0:1] - Channel indicator Bits
“01” indicates channel 2, and “10” indicates channel 3.
DBUS COMMUNICATIONS
registers. A CRC pattern is automatically appended to each
message. The data and CRC lengths are programmed by the
DnLENGTH register.
DBUS message.
status is stable), the RNE flag is set to indicate there is data
in the register available to be read.
DATA RATE
(CLK) and the values in the DnFSEL register. The CLK is
assumed to be 4MHz. The CLK is converted to a 64MHz
internal clock with a digital PLL, which is used to form the bit
rate clock. The minimum bit clock period which may be
programmed is:
requirements for minimum bit time. Longer base clock
periods can be selected by using the DxFSEL register. There
are 8 bits in the DxFSEL register representing values from 0
to 255. The complete equation for determining the base clock
period is:
f
CLK
Bit 0
Table 8. Examples of Base Data Rate
The bits indicate which bus channel the data came from.
The DBUS messages contain data from the DnH and DnL
At the end of a DBUS transfer (and after the CRC error
The base data rate is determined by the system clock
(1/16*f
However, this period may not meet overall system
((1/16*f
Table 8
Bit 8
DO8
= 4.0MHz.
00000000
00000001
00001101
00101000
11111110
11111111
FSEL
CLK
CLK
gives some examples of the base data rate for
Bit 9
DO9
CRC n
) x 320 = 5 usec
) x (320 +2x)) where x = 0 to 255
Bit
A0
10
Base Bit Period
Figure 20
……
LOGIC COMMANDS AND REGISTERS
(usec)
12.938
12.969
5.000
5.031
5.406
6.250
FUNCTIONAL DEVICE OPERATION
Bit
11
A1
shows the structure of the
A2
Bit
12
CRC 0
Base Bit Frequency
Bit
13
A3
(kbps)
200.0
198.8
184.9
160.0
77.3
77.1
C0
Bit
14
33781
Bit
C1
15
25