MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 27

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

message look like the CRC bits of an 8-bit response and
almost certainly would not be correct. Because the response
is incomplete and the CRC check is probably not valid, this
response is not useful.
normally only occurs after setting up the DBUS peripherals.
During address setup, a message with address 0000 is sent
to attempt to set the address of the next peripheral on the
daisy-chained bus. Before any peripherals have been
assigned an address, their bus switches are opened so the
addressing message only goes to the first peripheral in line.
As each peripheral gets an address, it closes its bus switch
so the next address assignment command can reach the next
LOGIC BLOCK DIAGRAM DESCRIPTION
the major logic blocks in the IC.
SPI0
This interface provides two-way communications between
the IC and an MCU. The MCU can write to registers that
control the operation of the IC, and read back the conditions
in the IC using the SPI. It can also write data to be sent out
on the DBUS, and read data that was returned on the DBUS.
The register pointer and bit pointer are used to control which
registers and bits are being written to, and read from using
Analog Integrated Circuit Device Data
Freescale Semiconductor
The long word to short word message size transition
Figure
The SPI0 is a standard slave serial peripheral interface.
PORB
RSTB
CLK 64
MHz
SCLK0
MOSI0
MISO0
SCLK1
MISO1
CSB0
CSB1
23, Logic Block Diagram, shows a block diagram of
CLOCK DIVIDERS
SPREADING and
test mode regs
FREQUENCY
check pattern
control regs
enable regs
length regs
spread dev
spread fsel
seed regs
reg pointer
bit pointer
poly regs
mask ID
SPI0
SPI1
16
data
5
10
4
16
data
1/3
data
stat
addr
RD
BIT CLOCK
SPI1 Registers
Figure 23. Logic Block Diagram
Addressed Rx Buffer
Addressed Tx Buffer
data
data
data
data
data
data
data
data
data
data
data
data
abort
enN
addr
addr
addr
addr
x pop
slave
addr
stat
stat
stat
stat
ptr
Tx not empty
peripheral in line on the bus. Each peripheral responds to an
address assignment only once (during the next message
after the command that set its address). After the last
peripheral has been assigned an address, any subsequent
address assignments will receive no response. When the
master MCU fails to receive a response, it knows it has
passed the last peripheral. At this point, short word messages
may be sent. The first such message will have no meaningful
response associated with it.
because there was no previous message, therefore there will
be no meaningful response during the first message transfer.
the SPI. Its operation is described in detail in the section
entitled
status registers. They are written and read using the SPI0
interface, and are affected by events in the IC. Detailed
descriptions of their operation and use can be found in
section
SPI1
asynchronously to the SPI0. It uses 16-bit transfers and is
read only. The MOSI function is not implemented. SPI1 only
reads the SPI1 8 16-bit circular buffer registers.
data
stat
push
data
pop
The first message after reset is also a special case,
The register set consists of transmit, receive, control, and
The SPI1 is a slave serial peripheral interface. It operates
16
4
SPI0 Register and Bit
SPI0 COMMUNICATIONS on page
16
Misc. Functions
STATE MACHINE
check
DBUS XFER
CRC
check
CRC
check
CRC
LOGIC COMMANDS AND REGISTERS
Filter
Filter
Filter
FUNCTIONAL DEVICE OPERATION
generate
Loop Sel
Loop
Mode
Mux
CRC
Descriptions.
Loop Sel
VSUP voltage
Filter
Filter
Bus switch
Sample
over temp
compare
BUS Driver/Receiver Logic
Filter
Filter
22.
DSISn
DSIFn
HZN
signal mode
over currentN
idle mode
over currentN
receiver lowN
over tempN
receiver highN
receiver sumN
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