MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 20

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7. Receiver Decision Logic
PSEUDO BUS SWITCHES
They allow one channel to communicate via two external bus
wire sets (D0H/D0L and DPH/DPL). There is a pseudo bus
switch on both the bus high and bus low driver. Upon device
reset the bus switches are open. This allows the master to
initialize devices on D0H/D0L. After all of these slaves are
initialized, the pseudo bus switches can be closed, allowing
the devices on DPH/DPL to be initialized.
by the BSWH and BSWL bits in the D0EN register. These bits
can also open the switch at any time.
shutdown protection. Once the thermal shutdown point is
reached, the bus switch is opened (becoming high-
impedance) and the BSWH and/or BSWL bit is cleared in the
channel 0 DEN register. If this occurs, the Pseudo Bus
Switches can only be closed again by setting the BSWH and/
or BSWL bit to a 1 with a write command to the channel 0
DEN register.
20
33781
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Out of Spec
Mode Noise
Conditions
Common
Bus Pin
Pseudo Bus Switches are provided on the Channel 0 bus.
The Pseudo Bus Switches can only be commanded closed
The Pseudo Bus Switches have independent thermal
SPREAD SPECTRUM
Normal
Fault H
Fault L
Fault
Fault
Fault
High 6 ± 1
Receiver
Bad CRC
Bad CRC
Bad CRC
Bad CRC
CRC Ok
CRC Ok
CRC Ok
CRC Ok
mA
Low 6 ± 1
Bad CRC
Bad CRC
Bad CRC
Bad CRC
Receiver
CRC OK
CRC Ok
CRC Ok
CRC Ok
mA
Sum 12 ±
Receiver
Bad CRC
Bad CRC
Bad CRC
Bad CRC
CRC OK
CRC Ok
CRC Ok
CRC Ok
6mA
H*L Not OK
H*L Not OK
Low XOR
High and
(bit/bit)
H*L Ok
H*L Ok
N/A
N/A
N/A
N/A
N/A
N/A
H*S Not OK
Sum XOR
High and
(bit/bit)
H*S Ok
interference (EMI) from the DBUS bus is due to the regular
periodic frequency of the data bits. At a steady bit rate, the
time period for each bit is the same, which results in a steady
fundamental frequency plus harmonics. This results in
undesired signals appearing at multiples of the frequency
that can be strong enough to interfere with a desired signal.
randomly changing the duration of each bit. This can
significantly reduce the amplitude by having the signal spend
a much smaller percentage of time at any specific frequency.
The signal strength of the fundamental and harmonics are
reduced directly by the percentage of time it spends on a
specific frequency.
the spreading of the signal independently for each channel,
while generating the bit clock timing for the channel. This is
done in the Spread Spectrum (SS) Block Diagram shown in
Figure
clock is created from the on board 4MHz oscillator using a
digital PLL. Multiples of this clock period (15.625 nsec) are
used to select the minimum channel bit time. The Spread
N/A
N/A
N/A
N/A
N/A
N/A
N/A
The dominant source of radiated electromagnetic
A significant decrease in radiated EMI can be achieved by
A circuit to do this is included in this IC, and can perform
To implement the channel bit clock a common 64MHz
12.
L*S Not OK
Sum XOR
Low and
(bit/bit)
L*S Ok
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Analog Integrated Circuit Device Data
ER Bit
0
1
0
1
0
1
1
0
1
1
0
1
Freescale Semiconductor
DnRnxData
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Sum0
Sum0
SPI0
High
High
High
High
High
High
High
High
High
High
DnRnxData
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Sum1
Sum1
SPI1
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low