MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 32

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DnRnH REGISTERS
registers, four for each of the buses, as shown in
When written to, the data is the high byte of a 9- to16-bit
command. When read, it is the high byte of a 9- to 16-bit
return on the DBUS. Writing to this register and the low byte
register without a framing error schedules a DBUS
transaction.
DnRnL REGISTERS
registers, four for each of the buses. When written to, the data
is the low byte of a 16-bit command. When in read, it is the
low byte of a 16-bit return on the DBUS. Writing to this
DnRnSTAT REGISTER
status of their associated DnRnH and DnRnl registers. The
values are latched when
status detected by these bits will not update the register until
ER–CRC Error Bit
that each buffer has a bit to indicate whether the data in that
buffer was received correctly. Whenever a received data
value is available in the DnRnH and DnRnL registers, the
associated CRC error status is available at ERn in the
associated DnRnSTAT register. The ER bit is set or cleared
32
33781
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
These are read/write registers. There are sixteen of these
These are read/write registers. There are sixteen of these
There are read-only registers. These registers cover the
• 0 = CRC value for the data in the read buffer was
• 1 = CRC value for the data in the read buffer was not
CRC errors are associated with each receive buffer, so
correct.
correct (data not valid).
SPI Data Bit
Read/Write
Reset
SPI Data Bit
Read/Write
Reset
SPI Data Bit
Read
Reset
CS0
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
is asserted low. Any changes of
ER
0
0
0
Figure 24. DnRnH Data Register Bit Assignments
Figure 25. DnRnL Data Register Bit Assignments
Figure 26. DnRnSTAT Register Bit Assignments
Bit 14
Bit 6
TE
6
0
6
0
6
1
Table
Bit 13
Bit 5
SDS
5
0
5
0
5
0
8.
Bit 12
RNE
Bit 4
4
0
4
0
4
0
short word of 8 bits is selected for this bus (MSn = 1), this
register must be written in the SPI burst sequence. When the
short word length is set at other than 8 bits, this register will
contain the bits above eight, starting with the ninth bit in the
least significant bit position of the register. Unused bit
positions are don’t care values.
register and the high byte register without a framing error,
schedules a DBUS transaction. The bit assignments are
shown in
burst transaction, that transaction is ignored.
CS0
updates will not occur. If this address is pointed to by the first
SPI0 byte of a SPI burst transaction, that transaction is
ignored.
whenever data is written from the DBUS into the DnRnH/L
receive registers. If Channel Thermal Shutdown or Idle and
SIgnal Mode Disable occur, these bits will be reset along with
the other channel register bits.
TE–Transmit Register Empty Bit
associated channel register high and/or low, but has not been
read for sending on the DBUS. The bit is set to 0 on the rising
The bit assignments are shown in
If this address is pointed to by the first SPI0 byte of a SPI
The bit assignments are shown in
• 0 = Transmit buffer not empty.
• 1 = Transmit buffer empty.
This bit indicates that data has been written to the
is de-asserted. This is done to ensure that partial
Bit 11
Bit 3
Figure 25
ICL
3
0
3
0
3
0
Bit 10
Bit 2
2
0
2
0
2
0
0
Analog Integrated Circuit Device Data
FIX0
Bit 9
Bit 1
1
0
1
0
1
0
Freescale Semiconductor
Figure
Figure 26.
24. Even if a
FIX1
Bit 8
Bit 0
0
0
0
0
0
1