MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 3

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. 33781 Pin Definitions
Analog Integrated Circuit Device Data
Freescale Semiconductor
A functional description of each Pin can be found in the Functional Pin Descriptions section beginning on
Pin
10
11
1
2
3
4
5
6
7
8
9
Pin Name
SCLK0
SCLK1
MOSI0
MISO0
MISO1
AGND
VDD
RST
CS0
CS1
VSS
Pin Function
Ground
Ground
Output
Output
Power
Reset
Input
Input
Input
Input
Input
TESTOUT
TESTIN
SCLK0
SCLK1
MOSI0
MISO0
MISO1
AGND
VDD
VCC
RST
VSS
VPP
CS0
CS1
CLK
SPI0 Serial Data Clock Clocks data in from and out to SPI0. MISO0 data changes on the negative
SPI0 Master Out Slave
SPI1 Serial Data Clock Clocks data out from SPI1. MISO1 data changes on the negative
SPI0 Master In Slave
SPI1 Master In Slave
SPI0 Chip Select
SPI1 Chip Select
Analog Ground
Digital Voltage
Formal Name
Digital Ground
Figure 3. 33781 Pin Connections
IC Reset
Out
Out
PIN CONNECTIONS
In
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A low level on this pin returns all registers to a known state as indicated
in the sections entitled
Communications.
transition of SCLK0. MOSI0 is sampled on the positive edge of SCLK0.
SPI data into SPI0. This data input is sampled on the positive edge of
SCLK0
SPI0 data sent to the MCU by this device. This data output changes on
the negative edge of SCLK0. When CS0 is high, this Pin is high-
impedance.
transition of SCLK1.
SPI1 data sent to the MCU by this device. This data output changes on
the negative edge of SCLK1. When CS1 is high, this Pin is high-
impedance.
When this signal is high, SPI signals on SPI0 are ignored. Asserting this
pin low starts an SPI0 transaction. The SPI0 transaction is signaled as
completed when this signal returns high.
Ground for the analog circuits. This pin is not connected internally to the
other grounds on the chip. It should be connected to a quiet ground on
the board.
When this signal is high, SPI signals on SPI1 are ignored. Asserting this
pin low starts an SPI1 transaction. The SPI1 transaction is signaled as
completed when this signal returns high.
Digital ground connected internally to the other on-chip grounds. This
ground is connected to circuits that will consume current during IDDQ
testing.
Output of the Internal 2.5V regulator for the digital circuits. No external
current draw is allowed from this pin.
32
31
30
29
28
27
26
25
23
22
21
20
19
18
17
24
GND
DPL
D0L
DPH
D0H
VSUP1
D1H
D1L
GND
D2L
D2H
VSUP2
D3H
D3L
GND
VSS_IDDQ
SPI0 Register and Bit Descriptions
Definition
PIN CONNECTIONS
page
15.
and
SPI1
33781
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