AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 1157

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• DSE: DAC Data Setup Extra Clock Cycle
• DDA: DAC Dual Data in Data Register A
• LP: DAC Low Power Reduction Mode
32117C–AVR-08/11
0: No extra clock latency.
1: Add an extra clock cycle latency between data written and start of conversion. This may be useful when the DAC clock is
running fast. Adding an extra clock cycle latency might help meeting the data setup time constraint.
0:No dual data in DR0.
1:Dual data in DR0. This allows writing two 16-bit wide data words in a single write operation to the DR0 register. In this case the
16 upper bits are assigned to the channel B data word while the lower 16 bits remain assigned to the channel A data word.
0: DAC low power mode disabled.
1: DAC low power mode enabled.
AT32UC3C
1157