AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 229

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.6.2
14.6.2.1
14.6.3
32117C–AVR-08/11
Event Shaper (EVS) Operation
Event Propagation Latency
Input Glitch Filter (IGF)
PEVC contains Event Shapers (EVS) for certain types of generators:
Each Event Shaper is responsible of shaping one input, prior to going through a PEVC channel:
Input Glitch Filtering can be turned on or off by writing to the Input Glitch Filter (IGF) field of the
corresponding Event Shaper Register (EVS).
When IGF is on, the incoming event is sampled periodically. The sampling clock is divided from
CLK_RCSYS by the value of the Input Glitch Filter Divider Register (IGFDR). IGF will filter out
spikes and propagate only incoming events that respect one of the following two conditions :
Both CLK_RCSYS and CLK_PEVC must be enabled to use Input Glitch Filtering.
Once a channel is setup, incoming peripheral events are relayed by hardware. Event progation
latency is therefore cycle deterministic. However, its value depends on the exact settings that
apply to a given channel.
When the channel multiplexer CHMXn.EVMX selects a generator without Event Shaper, event
propagation latency is 0 cycle. Software event is a particular case of 0 cycle propagation.
When the channel multiplexer CHMXn.EVMX selects a generator with Event Shaper, event
propagation latency depends on Input Glitch Filter setting EVSm.IGF :
Table 14-2.
Please refer to the Module Configuration section at the end of this chapter for the list of genera-
tors implementing Event Shapers.
Generator
CHMXn.EVMX
Generator without Event Shaper
Software event
Generator with Event Shaper
Generator with Event Shaper
• Asynchronous generators and/or external input
• General-purpose waveforms like timer outputs or Generic Clocks
• Synchronize asynchronous external inputs
• Apply any additional glich-filtering
• Detect rise, fall, or both edges of the incoming signal
• rise event : 2 samples low, followed by 0+ changes, followed by 2 samples high
• fall event : 2 samples high, followed by 0+ changes, followed by 2 samples low
• IGF off : event propagation latency is lesser or equal to 2 CLK_PEVC cycles
• IGF on : event propagation latency is lesser or equal to 3 *
Event Propagation Latency
Input Glitch Filter
EVSm.IGF
-
Off
On
-
Latency
0
0
2
3 * 2
2
IGFDR+1
IGFDR+1
* CLK_RCSYS cycles
AT32UC3C
Clock
-
-
CLK_PEVC
CLK_RCSYS
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