AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 168

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.6.1
Name:
Access Type:
Offset:
Reset Value:
• KEY
• TBAN: Time Ban Prescale Select
• CSSEL: Clock Source Select
• CEN: Clock Enable
• PSEL: Time Out Prescale Select
• FCD: Flash Calibration Done
• SFV: WDT Control Register Store Final Value
• MODE: WDT Mode
32117C–AVR-08/11
FCD
31
23
15
7
-
-
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads
as zero.
Counter bit TBAN is used as watchdog “banned” time frame. In this time frame clearing the WDT timer is forbidden, otherwise a
watchdog reset is generated and the WDT timer is cleared.
0: Select the system RC oscillator (RCSYS) as clock source.
1: Select the 32KHz crystal oscillator (OSC32K) as clock source.
0: The WDT clock is disabled.
1: The WDT clock is enabled.
Counter bit PSEL is used as watchdog timeout period.
This bit is set after any reset.
0: The flash calibration will be redone after a watchdog reset.
1: The flash calibration will not be redone after a watchdog reset.
0: WDT Control Register is not locked.
1: WDT Control Register is locked.
Once locked, the Control Register can not be re-written, only a reset unlocks the SFV bit.
0: The WDT is in basic mode, only PSEL time is used.
1: The WDT is in window mode. Total timeout period is now TBAN+PSEL.
Writing to this bit when the WDT is enabled has no effect.
Control Register
30
22
14
6
-
-
CTRL
Read/Write
0x000
0x00010080
29
21
13
5
-
-
TBAN
28
20
12
4
-
KEY
SFV
27
19
11
3
MODE
PSEL
26
18
10
2
CSSEL
DAR
25
17
9
1
AT32UC3C
CEN
EN
24
16
8
0
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