AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 899

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI shall be cleared by software to acknowledge the interrupt. This is done by writing a one
to the Transmitted OUT Data Interrupt Clear bit (UPCONnCLR.TXOUTIC), which does not affect
the pipe FIFO.
The user writes the OUT data to the bank referenced to by the PEPn descriptor and allows the
USBC to send the data by writing a one to the FIFO Control Clear (UPCONnCLR.FIFOCONC)
bit. This will also cause a switch to the next bank if the OUT pipe is composed of multiple banks.
The TXOUTI and FIFOCON bits will be updated accordingly
TXOUTI shall always be cleared before clearing FIFOCON to avoid missing an TXOUTI event.
Note that if the user decides to switch to the Suspend state (by writing a zero to UHCON.SOFE)
while a bank is ready to be sent, the USBC automatically exits this state and sends the data.
Figure 32-21. Example of an OUT pipe with one data bank
Figure 32-22. Example of an OUT pipe with two data banks and no bank switching delay
SW
SW
write data to CPU
write data to CPU
BANK 0
BANK 0
SW
OUT
SW
OUT
SW
(bank 0)
DATA
write data to CPU
BANK 1
(bank 0)
DATA
ACK
HW
HW
ACK
SW
OUT
SW
SW
write data to CPU
(bank 1)
DATA
write data to CPU
BANK 0
BANK0
AT32UC3C
ACK
SW
OUT
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