AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 321

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.6.5
18.6.5.1
18.6.5.2
32117C–AVR-08/11
Automatic Wait States
Chip select wait states
Early read wait state
_MSB:2]
, NBS1,
, A1
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the deactivation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..5], NRD lines are all set to high level.
Figure 18-15 on page 321
(NCS0) and Chip Select 2 (NCS2).
Figure 18-15. Chip Select Wait State Between a Read Access on NCS0 and a Write Access on
CLK_SMC
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
NCS0
NCS2
D[15:0]
NWE
NRD
NCS2
NRDCYCLE
illustrates a chip select wait state between access on Chip Select 0
Read to Write
Wait State
Chip Select
Wait State
NWECYCLE
AT32UC3C
321