AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 65

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.7.6
Name:
Access Type:
Offset:
Reset Value:
•
32117C–AVR-08/11
MASK: Clock Mask
31
23
15
7
-
-
-
-
If bit n is written to zero, the clock divided by 2
according to the current power mode.
Divided Clock Mask
30
22
14
6
-
-
PBADIVMASK/PBBDIVMASK/PBCDIVMASK
Read/Write
0x0040, 0x0044, 0x0048
-
Table 7-8.
Table 7-9.
Bit
0
1
2
3
4
5
6
Bit
0
1
2
3
29
21
13
5
-
-
-
USART0
PBA Divided Clock Mask
PBC Divided Clock Mask
USART1
Table 7-8
CLK_PBC_USART_DIV
(n+1)
CLK_PBA_USART_DIV
28
20
12
and
4
-
-
-
is stopped. If bit n is written to one, the clock divided by 2
Table 7-9
-
-
-
USART2
-
-
-
-
-
-
MASK[6:0]
show what clocks are affected by the different MASK bits.
27
19
11
USART4
3
-
-
-
USART3
26
18
10
2
-
-
-
TIMER0_CLOCK2
TIMER0_CLOCK3
25
17
9
1
-
-
-
TIMER1_CLOCK2
TIMER1_CLOCK3
TIMER1_CLOCK4
TIMER1_CLOCK5
TC0
AT32UC3C
-
-
TC1
(n+1)
-
-
-
is enabled
24
16
8
0
-
-
-
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