AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 941

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.3.2
Register Name:
Access Type:
Offset:
Reset Value:
Note:
• PnINT: Pipe n Interrupt
• HWUPI: Host Wakeup Interrupt
• HSOFI: Host Start of Frame Interrupt
• RXRSMI: Upstream Resume Received Interrupt
• RSMEDI: Downstream Resume Sent Interrupt
• RSTI: USB Reset Sent Interrupt
32117C–AVR-08/11
P7INT
31
23
15
7
-
-
-
1. PnINT bits are within the range from P0INT to P6INT.
This bit is cleared when the interrupt source is served.
This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe
interrupt enable bit is one (UHINTE register).
This bit is cleared when the HWUPIC bit is written to one.
This bit is set when:
- the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is detected.
- the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.
- the host controller is in the Idle state (VBUSRQ is zero, no VBUS is generated), and an SRP event initiated by the peripheral is
detected (USBSTA.SRPI is one).
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is cleared when the HSOFIC bit is written to one.
This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the
host controller in low speed mode, this bit is also set when a keep-alive is sent.
This bit is set when an Upstream Resume has been received from the Device.
This bit is cleared when the RXRSMIC is written to one.
This bit is cleared when the RSMEDIC bit is written to one.
This bit set when a Downstream Resume has been sent to the Device.
This bit is cleared when the RSTIC bit is written to one.
This bit is set when a USB Reset has been sent to the device.
(1)
Host Global Interrupt Register
P6INT
HWUPI
30
22
14
6
-
-
UHINT
Read-Only
0x0404
0x00000000
(1)
P5INT
HSOFI
29
21
13
5
-
-
(1)
RXRSMI
P4INT
28
20
12
4
-
-
(1)
RSMEDI
P3INT
27
19
11
3
-
-
(1)
P2INT
RSTI
26
18
10
2
-
-
(1)
P1INT
DDISCI
25
17
9
1
-
-
(1)
AT32UC3C
DCONNI
P8INT
P0INT
24
16
8
0
-
(1)
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