AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 110

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

18.3
18.3.1
18.3.2
110
Overview of the TWI Module
AT89LP3240/6440
SCL and SDA Pins
Bit Rate Generator Unit
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
The TWI module is comprised of several submodules, as shown in
drawn in a thick line are accessible through the AT89LP data bus.
Figure 18-9. Overview of the TWI Module
These pins interface the AT89LP TWI with the rest of the MCU system. The output drivers con-
tain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a
spike suppression unit removing spikes shorter than 50 ns.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR). Slave operation does not depend on the
Bit Rate setting, but the CPU clock frequency in the slave must be at least 16 times higher than
the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the
Address Match Unit
Slew-rate
Arbitration Detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
State Machine and
Control Unit
Status Control
Control Register
Bit Rate Generator
(TWCR)
Figure
Bit Rate Register
Prescaler
(TWBR)
18-9. All registers
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