AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 45

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

10. I/O Ports
10.1
3706C–MICRO–2/11
Port Configuration
The AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number of
I/O pins available depends on the clock and reset options as shown in
Table 10-1.
All port pins on the AT89LP3240/6440 may be configured to one of four modes: quasi-bidirec-
tional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port
modes may be assigned in software on a pin-by-pin basis as shown in
isters listed in
pins. When the fuse is enabled, all port pins default to input-only mode after reset. When the
fuse is disabled, all port pins, with the exception of the analog inputs, P0.7-0, P2.4, P2.5, P2.6
and P2.7, default to quasi-bidirectional mode after reset and are weakly pulled high. The analog
input pins always reset to input-only (tristate) mode. Each port pin also has a Schmitt-triggered
input for improved input noise rejection. During Power-down all the Schmitt-triggered inputs are
disabled with the exception of P3.2 (INT0), P3.3 (INT1), P4.2 (RST), P4.0 (XTAL1) and P4.1
(XTAL2) which may be used to wake up the device. Therefore, P3.2, P3.3, P4.2, P4.0 and P4.1
should not be left floating during Power-down. In addition any pin of Port 1 configured as a Gen-
eral-Purpose interrupt input will also remain active during Power-down to wake-up the device.
These interrupt pins should either be disabled before entering Power-down or they should not be
left floating.
.
Table 10-2.
.
Table 10-3.
Clock Source
External Crystal or
Resonator
External Clock
Internal RC Oscillator
PxM0.y
Port
0
0
1
1
0
1
2
3
4
I/O Pin Configurations
Table
Configuration Modes for Port x, Bit y
Port Configuration Registers
Port Data
P4 (C0H)
10-3. The Tristate-Port User Fuse determines the default state of the port
P0 (80H)
P1 (90H)
P2 (A0H)
P3 (B0H)
PxM1.y
0
1
0
1
Reset Option
External RST Pin
No external reset
External RST Pin
No external reset
External RST Pin
No external reset
Port Mode
Quasi-bidirectional
Push-pull Output
Input Only (High Impedance)
Open-Drain Output
Port Configuration
P0M0 (BAH), P0M1 (BBH)
P1M0 (C2H), P1M1 (C3H)
P2M0 (C4H), P2M1 (C5H)
P3M0 (C6H), P3M1 (C7H)
P4M0 (BEH), P4M1 (BFH)
Number of I/O Pins
35
36
36
37
37
38
AT89LP3240/6440
Table
Table 10-2
10-1.
using the reg-
45