AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 127

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

19.1
3706C–MICRO–2/11
Analog Input Muxes
also set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs
before using a comparator. When a comparator is first enabled, the comparator output and inter-
rupt flag are not guaranteed to be stable for 10 µs. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service. Before enabling the
comparators, the analog inputs should be tristated by putting P2.4, P2.5, P2.6 and P2.7 into
input-only mode. See
Each comparator may be configured to cause an interrupt under a variety of output value condi-
tions by setting the CMx
whenever the comparator outputs match the conditions specified by CMx
polled by software or may be used to generate an interrupt and must be cleared by software.
Both comparators share a common interrupt vector. If both comparators are enabled, the user
needs to read the flags after entering the interrupt service routine to determine which compara-
tor caused the interrupt.
The CAC
parator outputs. Normally the outputs are sampled every clock system; however, the outputs
may also be sampled whenever Timer 0, Timer 1 or Timer 2 overflows. These settings allow the
comparators to be sampled at a specific time or to reduce the number of comparator events
seen by the system when using level sensitive modes. The comparators will continue to function
during Idle mode. If this is not the desired behavior, the comparators should be disabled before
entering Idle. The comparators are always disabled during Power-down mode.
The positive input terminal of each comparator may be connected to any of the four analog input
pins by changing the CSA
input pins, the comparator must be disconnected from its inputs by clearing the CONA or CONB
bits. The connection is restored by setting the bits again after the muxes have been modified.
The corresponding comparator interrupt should not be enabled while the inputs are being
changed, and the comparator interrupt flag must be cleared before the interrupt is re-enabled in
order to prevent an unintentional interrupt request.
The equivalent model for the analog input circuitry is illustrated in
applied to AINn is subjected to the pin capacitance and input leakage of that pin, regardless of
whether that channel is selected as input to the comparator. When the channel is selected, the
source must drive the input capacitance of the comparator through the series resistance (com-
bined resistance in the input path).
SETB
CLR
ANL
...
ORL
ANL
1-0
EC
ACSRA, #0DFh ; Clear CONA to disconnect COMP A
ACSRA, #020h ; Set CONA to connect COMP A
ACSRA, #0EFh ; Clear any spurious interrupt
EC
and CBC
1-0
“Port Analog Functions” on page
2-0
bits in AREF control when the comparator interrupts sample the com-
1-0
bits in ACSRx. The comparator interrupt flags CFx in ACSRx are set
; Disable comparator interrupts
; Modify CSA or RFA bits
; Re-enable comparator interrupts
or CSB
1-0
bits in ACSRA and ACSRB. When changing the analog
48.
AT89LP3240/6440
Figure
20-3. An analog source
2-0.
The flags may be
127