AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 46
AT89LP3240
Manufacturer Part Number
AT89LP3240
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT89LP3240.pdf
(200 pages)
Specifications of AT89LP3240
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
38
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
4.25
Eeprom (bytes)
8192
Self Program Memory
IAP
Operating Voltage (vcc)
2.4 to 3.6
Timers
3
Isp
SPI/OCD
Watchdog
Yes
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10.1.1
10.1.2
46
AT89LP3240/6440
Quasi-bidirectional Output
Input-only Mode
Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-
bidirectional port can be used both as an input and output without the need to reconfigure the
port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an
external device to pull the pin low. When the pin is driven low, it is driven strongly and able to
sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the
pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin
high if it is left floating.
A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains
a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source
current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external
device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the
pin low under these conditions, the external device has to sink enough current to overpower the
weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-
high transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a
logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the
port pin high. The quasi-bidirectional port configuration is shown in
Figure 10-1. Quasi-bidirectional Output
The input only port configuration is shown in
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P3.2, P3.3, P4.2, P4.0 and P4.1 is not disabled during Power-down (see
fore these pins should not be left floating during Power-down when configured in this mode.
Figure 10-2. Input Only
Register
From Port
Input
Data
1 Clock Delay
(D Flip-Flop)
PWD
Figure
Input
Data
PWD
10-2. The output drivers are tristated. The
V
Strong
CC
Port
Pin
V
Weak
Very
CC
Figure
Figure
10-1.
V
Weak
CC
10-3) and there-
Port
Pin
3706C–MICRO–2/11
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