AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 32

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

6.2
6.3
6.4
6.5
32
External Clock Source
Internal RC Oscillator
System Clock Out
System Clock Divider
AT89LP3240/6440
The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly
by an external clock source as shown in
general purpose I/O P4.1, or configured to output a divided version of the system clock.
Figure 6-2.
The AT89LP3240/6440 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±2.5%. When
enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1 respectively.
XTAL2 may also be configured to output a divided version of the system clock. The frequency of
the oscillator may be adjusted within limits by changing the RC Calibration Byte stored at byte
128 of the User Signature Array. This location may be updated using the IAP interface (location
0180H in SIG space) or by an external device programmer (UROW location 0080H). See
tion 25.8 “User Signature and Analog Configuration” on page
calibration byte is stored at byte 8 of the Atmel Signature Array (0008H in SIG space).
When the AT89LP3240/6440 is configured to use either an external clock or the internal RC
oscillator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is
enabled by setting the COE bit in CLKREG. For example, setting COE = “1” when using the
internal oscillator will result in a 4.0 MHz (±2.5%) clock output on P4.1. P4.1 must be configured
as an output in order to use the clock out feature.
The CDV
source by powers of 2. The clock divider provides users with a greater frequency range when
using the Internal RC Oscillator. For example, to achieve a 1 MHz system frequency when using
the IRC, CDV
reduce power consumption by decreasing the operational frequency during non-critical periods.
The resulting system frequency is given by the following equation:
where f
for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-
ing normal execution. Changes to CDV are synchronized such that the system clock will not
OSC
2-0
is the frequency of the selected clock source. The clock divider will prescale the clock
bits in CLKREG allow the system clock to be divided down from the selected clock
2-0
External Clock Drive Configuration
should be set to 011B for divide-by-8 operation. The divider can also be used to
OSCILLATOR
NC, GPIO, or
EXTERNAL
CLKOUT
SIGNAL
Figure
f
SYS
=
6-2. XTAL2 may be left unconnected, used as
------------ -
2
f
OSC
CDV
XTAL2 (P4.1)
XTAL1 (P4.0)
GND
165. A copy of the factory
3706C–MICRO–2/11
Sec-