AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 141

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

21. Programmable Watchdog Timer
3706C–MICRO–2/11
The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig-
gering a system reset when it times out after the software has failed to feed the timer prior to the
timer overflow. By Default the WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and
PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K
clock cycles. The Timer Prescaler can also be used to lengthen the time-out period (see
6-2 on page
times out without being serviced, an internal RST pulse is generated to reset the CPU. See
Table 21-1
Table 21-1.
Note:
The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the
sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the
WDTEN bit in WDTCON will be set to “1”. To prevent the WDT from generating a reset when if
overflows, the watchdog feed sequence must be written to WDTRST before the end of the time-
out period. To feed the watchdog, two write instructions must be sequentially executed success-
fully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The
instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register.
An incorrect feed or enable sequence will cause an immediate watchdog reset. The program
sequence to feed or enable the watchdog timer is as follows:
PS2
1. The WDT time-out period is dependent on the system clock frequency.
0
0
0
0
1
1
1
1
for the available WDT period selections.
33) The WDT is disabled by Reset and during Power-down mode. When the WDT
MOV WDTRST, #01Eh
MOV WDTRST, #0E1h
Watchdog Timer Time-out Period Selection
WDT Prescaler Bits
Time-out Period
PS1
0
0
1
1
0
0
1
1
=
------------------------------------------------------ -
Oscillator Frequency
2
PS0
(
0
1
0
1
0
1
0
1
PS
+
14
)
×
AT89LP3240/6440
(
TPS
+
(Clock Cycles)
1
)
Period
1024K
2048K
128K
256K
512K
16K
32K
64K
(1)
Table
141