AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 119

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 18-7.
3706C–MICRO–2/11
Status
Code
(TWSR)
08h
10h
38h
40h
48h
50h
58h
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
Arbitration lost in SLA+R or
NOT ACK bit
SLA+R has been
transmitted; ACK has been
received
SLA+R has been
transmitted; NOT ACK has
been received
Data byte has been
received; ACK has been
returned
Data byte has been
received; NOT ACK has
been returned
Status Codes for Master Receiver Mode
TWEN must be written to one to enable the Two-wire Serial Interface, STA must be written to
one to transmit a START condition and TWIF must be cleared. The TWI will then test the Two-
wire Serial Bus and generate a START condition as soon as the bus becomes free. After a
START condition has been transmitted, the TWIF flag is set by hardware, and the status code in
TWSR will be 08h (see
This is done by writing SLA+R to TWDR. Thereafter the TWIF bit should be cleared to continue
the transfer.
When SLA+R has been transmitted and an acknowledgment bit has been received, TWIF is set
again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 38h, 40h or 48h. The appropriate action to be taken for each of these status codes is
detailed in
is set high by hardware. This scheme is repeated until the last byte has been received. After the
last byte has been received, the MR should inform the ST by sending a NACK after the last
received data byte. The transfer is ended by generating a STOP condition or a repeated START
condition.
To/from TWDR
Load SLA+R
Load SLA+R
Load SLA+W
No action
No action
No action
No action
No action
No action
No action
Read data byte
Read data byte
Read data byte
Read data byte
Read data byte
Table
Application Software Response
18-7. Received data can be read from the TWDR Register when the TWIF flag
Table
STA
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
18-7). In order to enter MR mode, SLA+R must be transmitted.
STO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
To TWCR
TWIF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AA
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
Next Action Taken by TWI Hardware
SLA+R will be transmitted; ACK or NOT ACK
will be received
SLA+R will be transmitted; ACK or NOT ACK
will be received
SLA+W will be transmitted; Logic will switch to
Master Transmitter mode
Two-wire Serial Bus will be released and not
addressed Slave mode will be entered
A START condition will be transmitted when the
bus becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
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