AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 136

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

20.2
136
DAC Operation
AT89LP3240/6440
Figure 20-3. Equivalent Analog Input Model
The DAC converts a 10-bit signed digital value to an analog output current through successive
approximation. The DAC always operates in differential mode, outputting a differential current
between its positive (P2.2) and negative (P2.3) outputs with a common mode voltage of V
The minimum value represents zero difference and the maximum values represent a difference
of positive or negative V
convert the current into a voltage suitable for driving other circuits.
The DAC is enabled by setting the ADCE and DAC bits in DADC. Some settling time is required
for the reference circuits to stabilize after the DAC is enabled. The DAC does not have multiple
output channels and the DIFF, ACON and ACS bits have no effect in DAC mode. P2.2 and P2.3
are automatically forced to input-only mode while the DAC is enabled.
A timing diagram of a DAC conversion is shown in
clock cycles to complete. Construction of the analog output starts in the second cycle of the con-
version and the DAC will allow the new value to propagate to the outputs during cycle 7, after the
5 MSBs are complete. At the end of the conversion, the interrupt flag is set. An additional 1 ADC
clock cycle and up to 2 system clock cycles may be required to synchronize ADIF with the rest of
the system. The DADL and DADH registers hold the value to be output and are write-only during
DAC mode. An internal buffer samples DADH/DADL at the start of the conversion and holds the
value constant for the remainder of the conversion. One system clock cycle is required to trans-
fer the contents of DADH/DADL into the buffer at the start of the conversion and therefore the
ADC clock frequency must always be equal to or less than the system clock frequency during
DAC mode to ensure that the buffer is updated before the second cycle.
Figure 20-4. DAC Timing Diagram
The equivalent model for the analog output circuitry is illustrated in
put resistance of the DAC must drive the pin capacitance and any external load on the pin.
Cycle Number
ADC Clock
GO/BSY
ADIF
DADH
DADL
ADCn
1
C
10 pF
PIN
2
Initialize Circuitry
REF
=
3
minus 1 LSB. An external transimpedance amplifier is required to
MSB of Output
LSB of Output
Begin Output
4
One Conversion
5
6
10 kΩ
R
IN
7
=
8
Figure
Conversion
Complete
9
20-4. The conversion requires 11 ADC
10
R
10 kΩ
MUX
11
=
Figure
Next Conversion
1
20-5. The series out-
C
2 pF
S/H
2
Initialize
=
3706C–MICRO–2/11
3
DD
/2.