AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 61

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

12.1
Table 12-3.
Table 12-4.
3706C–MICRO–2/11
T2CON Address = 0C8H
Bit Addressable
Bit
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2MOD Address = 0C9H
Not Bit Addressable
Symbol
PHSD
Bit
Timer 2 Registers
PHSD
TF2
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1) or dual-slope mode.
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
7
Function
CCA Phase Direction. For phase modes with 3 or 4 channels, PHSD determines the direction that the channels are
cycled through. PHSD also determines the initial phase relationship for 2 phase modes.
PHSD
0
1
7
T2CON – Timer/Counter 2 Control Register
T2MOD – Timer 2 Mode Control Register
Direction
EXF2
A
B
PHS2
Control and status bits for Timer 2 are contained in registers T2CON (see
T2MOD (see
16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and
0CAH are the 16-bit Capture/Reload register for Timer 2 in capture and auto-reload modes.
6
→ → →
→ → →
6
B
A
A
B
B
A
RCLK
PHS1
or
or
5
Table
5
A
C
→ → → → →
→ → → → →
12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the
B
B
C
A
TCLK
PHS0
4
4
A
C
B
B
C
A
EXEN2
T2CM1
or
or
3
3
A
D
→ → → → → → →
→ → → → → → →
B
C
T2CM0
C
B
TR2
2
2
D
A
A
D
AT89LP3240/6440
Reset Value = 0000 0000B
Reset Value = 0000 0000B
B
C
T2OE
C/T2
C
1
B
1
D
A
DCEN
CP/RL2
Table
0
0
12-3) and
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