AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 37

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 8-1.
8.2
8.2.1
3706C–MICRO–2/11
Symbol
SMOD1
SMOD0
PWDEX
POF
GF1, GF0
PD
IDL
PCON = 87H
Not Bit Addressable
Bit
Power-down Mode
Interrupt Recovery from Power-down
Function
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
General-purpose Flags
Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automatically by hardware when
waking up from power-down.
Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically by hardware when
waking up from idle
PCON
SMOD1
7
– Power Control Register
.
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once V
reduced. Power-down may be exited by external reset, power-on reset, or certain enabled
interrupts.
Three external interrupt sources may be configured to terminate Power-down mode: external
interrupts INT0 (P3.2) and INT1 (P3.3); and the general-purpose interrupts (GPI). To wake up by
external interrupt INT0 or INT1, that interrupt must be enabled by setting EX0 or EX1 in IE and
must be configured for level-sensitive operation by clearing IT0 or IT1. Any General-purpose
interrupt on Port 1 (GPI
and configured for level-sensitive detection, and EGP in IE2 must be set in order to terminate
Power-down.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed as shown in
At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see
The interrupt pin need not remain low for the entire time-out period.
SMOD0
6
PWDEX
5
7-0
) can also wake up the device. The GPI pin must be enabled in GPIEN
POF
4
GF1
3
GF0
2
AT89LP3240/6440
Reset Value = 000X 0000B
PD
1
Table 7-1 on page
IDL
0
DD
Figure
has been
8-1.
35).
37