AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 25

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

5.2
3706C–MICRO–2/11
Enhanced Dual Data Pointers
The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. This
two-byte instruction requires nine clock cycles to complete. The operand registers are not modi-
fied by the instruction and the result is stored in the 40-bit M register. MAC AB also updates the
C and OV flags in PSW. C represents the sign of the MAC result and OV is the two’s comple-
ment overflow. Note that MAC AB will not clear OV if it was previously set to one.
Three additional extended instructions operate directly on the M register. CLR M (A5 E4H)
clears the entire 40-bit register in two clock cycles. LSL M (A5 23H) and ASR (A5 03H) shift M
one bit to the left and right respectively. Right shifts are done arithmetically, i.e. the sign is
preserved.
The 40-bit M register is accessible 16-bits at a time through a sliding window as shown in
5-5. The MRW
through the MACL and MACH addresses. For normal fixed point operations the window can be
fixed to the rank of interest. For example, multiplying two 1.15 format numbers places a 2.30 for-
mat result in the M register. If MRW is set to 10B, a 1.15 value is obtained after performing a
single LSL M.
Figure 5-5.
As a consequence of the MAC unit, the standard 8x8 MUL AB instruction can support signed
multiplication. The SMLA and SMLB bits in DSPR control the multiplier’s interpretation of the
ACC and B registers, allowing any combination of signed and unsigned operand multiplication.
These bits have no effect on the MAC operation which always multiplies signed-by-signed.
The AT89LP3240/6440 provides two 16-bit data pointers: DPTR0 formed by the register pair
DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H
and 85H). The data pointers are used by several instructions to access the program or data
memories. The Data Pointer Configuration Register (DPCF) controls operation of the dual data
pointers
erenced by instructions including the DPTR operand. Each data pointer may be accessed at its
respective SFR addresses regardless of the DPS value. The AT89LP3240/6440 provides two
methods for fast context switching of the data pointers:
• Bit 2 of DPCF is hard-wired as a logic 0. The DPS bit may be toggled (to switch data pointers)
simply by incrementing the DPCF register, without altering other bits in the register
unintentionally. This is the preferred method when only a single data pointer will be used at
one time.
EX:
(Table 5-5 on page
INC
M
M Register with Sliding Window
1-0
bits in DSPR
39 – 32
DPCF
MACH
Byte 4
; Toggle DPS
28). The DPS bit in DPCF selects which data pointer is currently ref-
31 – 24
MACH
MACL
Byte 3
(Table
5-1) select which 16-bit segment is currently accessible
23 – 16
MACH
MACL
Byte 2
MACH
15 – 8
MACL
Byte 1
AT89LP3240/6440
MACL
7 – 0
Byte 0
MRW
MRW
MRW
MRW
1-0
1-0
1-0
1-0
= 00B
= 01B
= 10B
= 11B
Figure
25