AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 128

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

19.2
19.3
128
Internal Reference Voltage
Comparator Interrupt Debouncing
AT89LP3240/6440
Figure 19-2. Equivalent Analog Input Model
The negative input terminal of each comparator may be connected to an internal voltage refer-
ence by changing the RFB
set to 1.3 V ±5%. The voltage reference also provides two additional voltage levels approxi-
mately 100 mV above and below V
as an internally referenced window comparator with up to four input channels. Changing the ref-
erence input must follow the same routine used for changing the positive input as described in
“Analog Input Muxes”
The comparator output is normally sampled every clock cycle. The conditions on the analog
inputs may be such that the comparator output will toggle excessively. This is especially true if
applying slow moving analog inputs. Three debouncing modes are provided to filter out this
noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modu-
late its sampling time when CxC
waits until two Timer 1 overflows have occurred before resampling the output. If the new sample
agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be
tuned by adjusting the time-out period of Timer 1. Because Timer 1 is free running, the
debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out
period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out
periods later. See
flows, i.e. CxC
be accepted as an edge event.
Figure 19-3. Negative Edge with Debouncing Example
Timer 1 Overflow
Comparator Out
AINn
1-0
!= 00B, any change in the comparator output must be valid after 4 samples to
Figure
CFx
C
10 pF
PIN
above.
Start
19-3. When the comparator clock is provided by one of the timer over-
=
1-0
or RFA
1-0
AREF
= 00B. When a relevant transition occurs, the comparator
1-0
. These levels may be used to configure the comparators
bits in AREF. The internal reference voltage, V
(rejected)
Compare
10 kΩ
R
IN
=
Start
R
10 kΩ
MUX
=
(accepted)
Compare
C
0.3 pF
CMP
<
3706C–MICRO–2/11
AREF
, is