adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet
adsp-bf539bbcz-5f8
Related parts for adsp-bf539bbcz-5f8
adsp-bf539bbcz-5f8 Summary of contents
Page 1
... SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K 16-bit or 256K 16-bit flash memory (ADSP-BF539F only) Memory management unit providing memory protection PERIPHERAL ACCESS BUS TWI0-1 CAN 2.0B GPIO PORT DMA CORE ...
Page 2
... ADSP-BF539/ADSP-BF539F TABLE OF CONTENTS General Description ................................................. 3 Low Power Architecture ......................................... 3 Automotive Products ............................................. 3 System Integration ................................................ 3 ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 3 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 4 DMA Controllers .................................................. 9 Real-Time Clock ................................................... 9 Watchdog Timer .................................................. 9 Timers ............................................................. 10 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Ports ...................... 10 2-Wire Interface ................................................. 11 UART Ports ...................................................... 11 Programmable I/O Pins ........................................ 11 Parallel Peripheral Interface ...
Page 3
... I/O, and general-purpose flag pins. ADSP-BF539/ADSP-BF539F PROCESSOR 64K bytes PERIPHERALS The ADSP-BF539/ADSP-BF539F processors contain a rich set 32K bytes of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as 32K bytes excellent overall system performance (see ...
Page 4
... C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF539/ADSP-BF539F processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space ...
Page 5
... R1.H R1.L R0.H R0.L Internal (On-Chip) Memory The ADSP-BF539/ADSP-BF539F processor has three blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory, consisting of 80K bytes SRAM, of which 16K bytes can be configured as a four-way set- associative cache. This memory is accessed at full processor speed. ...
Page 6
... The ADSP-BF539F4 contains a 4M bit (256K boot sector Spansion S29AL004D known good die flash mem- † ory . The ADSP-BF539F8 contains an 8M bit (512K bottom boot sector Spansion S29AL008D known good die flash memory. Features include the following: • Access times as fast (EBIU registers be set appropriately) • ...
Page 7
... Of these general-purpose interrupts, the two lowest priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF539/ADSP-BF539F pro- cessors. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities ...
Page 8
... MDMA1 Stream 0 Interrupt MDMA1 Stream 1 Interrupt Software Watchdog Timer Event Control The ADSP-BF539/ADSP-BF539F processors provide the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC Interrupt Latch Register (ILAT) – The ILAT register indicates when events have been latched ...
Page 9
... The stopwatch function counts down from a programmed value, with one second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSP- BF539/ADSP-BF539F processor from sleep mode upon genera- tion of any RTC wake-up event. Additionally, an RTC wake-up ...
Page 10
... If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF539/ADSP-BF539F pro- cessor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register ...
Page 11
... The ADSP-BF539/ADSP-BF539F processor has numerous peripherals that may not all be required for every application. Many of the pins thus have a secondary function, as program- mable I/O pins. There are two types of programmable I/O pins on the ADSP-BF539/ADSP-BF539F processor, with slightly dif- ferent functionality: programmable flags and general-purpose I/O. Programmable Flags (PFx) The ADSP-BF539/ADSP-BF539F processors have 16 bidirec- tional, general-purpose programmable flag (PF15– ...
Page 12
... MXVR pins after reset but can be reconfig- ured as GPIO pins through software. PARALLEL PERIPHERAL INTERFACE The ADSP-BF539/ADSP-BF539F processors provide a parallel peripheral interface (PPI) that can connect directly to parallel A/D and D/A converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedi- cated input clock pin frame synchronization pins, and data pins ...
Page 13
... BF539F processors from sleep mode when a wake-up preamble is received over the network or based on any other MXVR inter- rupt event. Additionally, detection of network activity by the MXVR can be used to wake up the ADSP-BF539/ADSP-BF539F processors from sleep mode and wake up the on-chip internal voltage regulator from the powered-down hibernate state. These ...
Page 14
... Rev Page February 2008 ) provide the lowest static power DDINT is still supplied in this mode, all of DDEXT Table 6, the ADSP-BF539/ADSP-BF539F proces- power domain supplies the RTC I/O and DDRTC power domain supplies all internal logic DDINT power domain supplies all I/O except for ...
Page 15
... The regulator controls the internal † See Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors (EE-228). logic voltage levels and is programmable with the voltage regu- lator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regula- ...
Page 16
... Table 8. Core Clock Ratios Signal Name CSEL1– BOOTING MODES The ADSP-BF539/ADSP-BF539F processors have three mecha- nisms (listed in instruction memory after a reset. A fourth mode is provided to “COARSE” ADJUSTMENT execute from external memory, bypassing the boot sequence. ON-THE-FLY Table 9. Booting Modes ÷ CCLK BMODE1– ...
Page 17
... Boot from 8-bit or 16-bit external flash memory – The 8-bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0. For ADSP-BF539F processors, if FCE is connected to AMS0, then the on-chip flash is booted. All configuration settings are set for the slowest device possible (3-cycle hold time; ...
Page 18
... EXAMPLE CONNECTIONS AND LAYOUT CONSIDERATIONS Figure 9 shows an example circuit connection of the ADSP- BF539/ADSP-BF539F to a MOST network. This diagram is intended as an example, and exact connections and recom- mended circuit values should be obtained from Analog Devices. Rev Page February 2008 ...
Page 19
... MLF R1 220 C2 0. 0.1 F MXEGND Figure 9. Example Connections of ADSP-BF539/ADSP-BF539F to MOST Network MXVR BOARD LAYOUT GUIDELINES MLF pin • Capacitors: C1: 0.1 μF (PPS type, 2% tolerance recommended) C2: 0.01 μF (PPS type, 2% tolerance recommended) • Resistor: R1: 220 Ω (1% tolerance) • The RC network connected to the MLF pin should be located physically close to the MLF pin on the board. • ...
Page 20
... All internal and I/O power supplies should be well bypassed with bypass capacitors placed as close to the ADSP- BF539/ADSP-BF539F as possible. For further details on the on-chip voltage regulator and related ...
Page 21
... PIN DESCRIPTIONS ADSP-BF539/ADSP-BF539F processor pin definitions are listed in Table 10. All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins, which are driven high active, then the memory pins are also three-stated. All unused I/O pins have their input buffers disabled with the Table 10 ...
Page 22
... ADSP-BF539/ADSP-BF539F Table 10. Pin Descriptions (Continued) Pin Name Type Description Parallel Peripheral Interface Port/GPIO PF0/SPI0SS I/O PF1/SPI0SEL1/TACLK I/O PF2/SPI0SEL2 I/O PF3/SPI0SEL3/PPI_FS3 I/O PF4/SPI0SEL4/PPI15 I/O PF5/SPI0SEL5/PPI14 I/O PF6/SPI0SEL6/PPI13 I/O PF7/SPI0SEL7/PPI12 I/O PF8/PPI11 I/O PF9/PPI10 I/O PF10/PPI9 I/O PF11/PPI8 I/O PF12/PPI7 I/O PF13/PPI6 I/O PF14/PPI5 I/O PF15/PPI4 I/O PPI3–0 I/O PPI_CLK/TMRCLK I Controller Area Network CANTX/PC0 I CAN Transmit/GPIO CANRX/PC1 I/ Media Transceiver (MXVR)/ ...
Page 23
... SPORT2 Receive Serial Clock/GPIO SPORT2 Receive Frame Sync/GPIO SPORT2 Receive Data Primary/GPIO SPORT2 Receive Data Secondary/GPIO SPORT2 Transmit Serial Clock/GPIO SPORT2 Transmit Frame Sync/GPIO SPORT2 Transmit Data Primary/GPIO SPORT2 Transmit Data Secondary/GPIO Rev Page February 2008 ADSP-BF539/ADSP-BF539F Driver Type ...
Page 24
... ADSP-BF539/ADSP-BF539F Table 10. Pin Descriptions (Continued) Pin Name Type Description Serial Port3 RSCLK3/PE8 I/O RFS3/PE9 I/O DR3PRI/PE10 I/O DR3SEC/PE11 I/O TSCLK3/PE12 I/O TFS3/PE13 I/O DT3PRI /PE14 I/O DT3SEC/PE15 I/O SPI0 Port MOSI0 I/O MISO0 I/O SCK0 I/O SPI1 Port MOSI1/PD0 I/O MISO1/PD1 I/O SCK1/PD2 I/O SPI1SS/PD3 I/O SPI1SEL1/PD4 I/O SPI2 Port MOSI2 /PD5 I/O MISO2/PD6 I/O SCK2/PD7 I/O SPI2SS/PD8 I/O SPI2SEL1/PD9 I/O UART0 Port ...
Page 25
... Internal Power Supply Real-Time Clock Power Supply MXVR Internal Power Supply MXVR External Power Supply MXVR Ground Ground 51. Figure 47 on Page 53 and Figure 48 on Page 54 apply when configured as an output. Rev Page February 2008 ADSP-BF539/ADSP-BF539F Driver Type C C Figure 34 on Page 50 and 1 ...
Page 26
... ADSP-BF539/ADSP-BF539F SPECIFICATIONS Component specifications are subject to change without notice. OPERATING CONDITIONS Parameter Internal Supply Voltage DDINT 3 V External Supply Voltage DDEXT V Real-Time Clock Power Supply DDRTC Voltage 4 V High Level Input Voltage High Level Input Voltage IH5V 6 V High Level Input Voltage ...
Page 27
... DDINT JUNCTION 25° DDINT JUNCTION = 0. MHz, T DDINT CCLK = 1 533 MHz, T DDINT CCLK 25°C DDRTC JUNCTION Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Typ 2.4 Maximum DD Maximum DD Maximum MHz 32 SCLK = 25°C 47 JUNCTION = 25°C ...
Page 28
... Rev Page February 2008 Figure 10 and Table 12 Ordering Guide on Page 60. a ADSP-BF539 tppZccc vvvvvv.x n.n yyww country_of_origin B Figure 10. Product Information on Package Field Description Automotive Grade (Optional) Temperature Range Package Type RoHS Compliant Part See Ordering Guide Assembly Lot Code ...
Page 29
... TIMING SPECIFICATIONS Table 13 describes the timing requirements for the ADSP-BF539/ADSP-BF539F processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock, and voltage-controlled Table 13. Core Clock (CCLK) Requirements Parameter Description f CLK Frequency (V = 1.2 V Minimum) ...
Page 30
... ADSP-BF539/ADSP-BF539F Clock and Reset Timing Table 16 and Figure 11 describe clock and reset operations. Per Absolute Maximum Ratings on Page 28, combinations of CLKIN and clock multipliers must not select core/peripheral clocks that exceed maximum operating conditions. Table 16. Clock and Reset Timing Parameter Timing Requirements ...
Page 31
... AOE ARE ARDY DATA15–0 Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY and Figure PROGRAMMED READ ACCESS 4 CYCLES BE, ADDRESS SARDY t HARDY Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max 2.1 0.8 4.0 0.0 6.0 0.8 HOLD 1 CYCLE ACCESS EXTENDED 3 CYCLES HARDY t t SARDY ...
Page 32
... ADSP-BF539/ADSP-BF539F Table 18. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA t Output Delay After CLKOUT ...
Page 33
... Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY and Figure ACCESS PROGRAMMED WRITE HOLD EXTENDED ACCESS 2 CYCLES 1 CYCLE 1 CYCLE BE, ADDRESS SARDY t t HARDY HARDY Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max 4.0 0.0 6.0 1.0 6.0 0 DDAT Unit ...
Page 34
... ADSP-BF539/ADSP-BF539F Table 20. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT ...
Page 35
... DATA(OUT) CMND ADDR (OUT SCLK t SSDAT t HSDAT t DCAD t ENSDAT t DCAD t HCAD NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 16. SDRAM Interface Timing Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max 2.1 0.8 7.5 2.5 2.5 6.0 0.8 6.0 1.0 t SCLKH t SCLKL t D SDA T t HCAD Unit ns ns ...
Page 36
... ADSP-BF539/ADSP-BF539F External Port Bus Request and Grant Cycle Timing Table 22 and Table 23 on Page 37 and Figure 17 on Page 37 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 22. External Port Bus Request and Grant Cycle Timing with Synchronous BR ...
Page 37
... CLKOUT High to BGH Deasserted Hold Time EBH CLKOUT BR AMSx ADDR19-1 ABE1-0 AWE ARE BG BGH Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR t WBR Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max 2 t SCLK 4.5 4.5 3.6 3.6 3.6 3 DBG t ...
Page 38
... ADSP-BF539/ADSP-BF539F Parallel Peripheral Interface Timing Table 24 and Figure 19, Figure 20, Figure describe Parallel Peripheral Interface operations. Table 24. Parallel Peripheral Interface Timing Parameter Timing Requirements t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK t External Frame Sync Setup Before PPI_CLK SFSPE t External Frame Sync Hold After PPI_CLK ...
Page 39
... DATA1 IS DATA0 SAMPLED t HFSPE t SFSPE t HDRPE Figure 20. PPI GP Rx Mode with External Frame Sync Timing FRAME DATA0 IS SYNC IS DRIVEN SAMPLED OUT t HFSPE SFSPE t HDTPE DATA0 t DDTPE Figure 21. PPI GP Tx Mode with External Frame Sync Timing Rev Page February 2008 ADSP-BF539/ADSP-BF539F ...
Page 40
... ADSP-BF539/ADSP-BF539F FRAME SYNC IS DRIVEN OUT PPI_CLK POLC = 0 PPI_CLK POLC = 1 t DFSPE t HOFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA DATA0 IS DRIVEN OUT t DDTPE t HDTPE DATA0 Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing Rev Page February 2008 ...
Page 41
... DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. Figure 23 on Page Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max 1 3.0 1 3.0 3.0 3.0 4.5 15.0 2 10.0 2 0.0 10.0 0.0 Min Max 1 8.0 1 –1.5 8.0 – ...
Page 42
... ADSP-BF539/ADSP-BF539F Table 28. External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 0 DDTLFSE t Data Enable from Late FS or MCE = 1, MFD = 0 DTENLFS 1 MCE = 1, TFSx enable and TFSx valid follow t DTENLFS 2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > t DATA RECEIVE— ...
Page 43
... DTENLFS 1ST BIT DTx t DDTLFSE LATE EXTERNAL TFSx DRIVE SAMPLE TSCLKx t SFSE/I TFSx t DTENLFS DTx 1ST BIT t DDTLFSE Figure 24. External Late Frame Sync Rev Page February 2008 ADSP-BF539/ADSP-BF539F DRIVE t HOFSE/I t DDTTE/I t DTENE/I 2ND BIT DRIVE t HOFSE/I t DDTTE/I t DTENE/I 2ND BIT ...
Page 44
... ADSP-BF539/ADSP-BF539F Serial Peripheral Interface Ports — Master Timing Table 29 and Figure 25 describe SPI ports master operations. Table 29. Serial Peripheral Interface (SPI) Ports—Master Timing Parameter Timing Requirements t Data Input Valid to SCKx Edge (Data Input Setup) SSPIDM t SCKx Sampling Edge to Data Input Invalid ...
Page 45
... HDSPID DDSPID MSB SSPID HSPID MSB VALID t DDSPID MSB t SSPID MSB VALID LSB VALID Figure 26. Serial Peripheral Interface (SPI) Ports—Slave Timing Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max 2t –1.5 SCLK 2t –1.5 SCLK 4t –1.5 SCLK 2t –1.5 SCLK 2t –1.5 SCLK 2t – ...
Page 46
... ADSP-BF539/ADSP-BF539F General-Purpose Port Timing Table 31 and Figure 27 describe general-purpose operations. Table 31. General-Purpose Port Timing Parameter Timing Requirement t GP Port Pin Input Pulse Width WFI Switching Characteristic t GP Port Pin Output Delay from CLKOUT Low GPOD CLKOUT GPP OUTPUT GPP O/D OUTPUT GPP INPUT ...
Page 47
... CLKOUT TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) 1 (Measured in SCLK Cycles) 1 (Measured in SCLK Cycles) t HTO Figure 28. Timer PWM_OUT Cycle Timing Rev Page February 2008 ADSP-BF539/ADSP-BF539F Min Max – 1) Unit SCLK SCLK SCLK ...
Page 48
... ADSP-BF539/ADSP-BF539F JTAG Test And Emulation Port Timing Table 33 and Figure 29 describe JTAG port operations. Table 33. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
Page 49
... Parameter Timing Requirements FS MXI Clock Frequency Stability MXI FT MXI Frequency Tolerance Over Temperature MXI DC MXI Clock Duty Cycle MXI kHz 38.912 Rev Page February 2008 ADSP-BF539/ADSP-BF539F fs = 44.1 kHz kHz 45.1584 49.152 Min Max –50 +50 –300 +300 40 60 Unit MHz ...
Page 50
... ADSP-BF539/ADSP-BF539F OUTPUT DRIVE CURRENTS The following figures show typical current-voltage characteris- tics for the output drivers of the ADSP-BF539/ADSP-BF539F processor. The curves represent the current drive capability of the output drivers as a function of output voltage. 120 100 100 0 0.5 1.0 1.5 SOURCE VOL TAGE (V) Figure 30 ...
Page 51
... 3. 3. 3.5 4 2.75V 2.0 2.5 3.0 ) Rev Page February 2008 ADSP-BF539/ADSP-BF539F 1.0 1.5 2.0 2 SOURCE VOLTAGE (V) Figure 39. Drive Current E (High V ) DDEXT V OL 4.0 3.5 ...
Page 52
... ADSP-BF539/ADSP-BF539F POWER DISSIPATION Many operating conditions can affect power dissipation. System designers should refer to Estimating Power for ADSP- BF538/ADSP-BF539 Blackfin Processors (EE-298) on the Analog Devices, Inc. website (www.analog.com)—use site search on “EE-298.” This document provides detailed information for optimizing your design for lowest power. ...
Page 53
... Figure 46. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for 30 25 200 250 Figure 47. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Rev Page February 2008 ADSP-BF539/ADSP-BF539F RISE TIME FALL TIME 0 50 100 150 LOAD CAPACITANCE (pF) Driver 2.7 V (MIN) DDEXT RISE TIME ...
Page 54
... ADSP-BF539/ADSP-BF539F RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 3.65 V (MAX) DDEXT RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 49 ...
Page 55
... JA θ 1 linear m/s air flow JMA θ 2 linear m/s air flow JMA θ JC Ψ 0 linear m/s air flow JT Ψ 1 linear m/s air flow JT Ψ 2 linear m/s air flow for can be used for a first ) P D Typical Unit 21.6 C/W 18.8 C/W 18.1 C/W 5.36 C/W 0.13 C/W 0.25 C/W 0.25 C/W Typical Unit 20.9 C/W 18.1 C/W 17.4 C/W 5.01 C/W 0.12 C/W 0.24 C/W 0.24 C/W Rev Page February 2008 ADSP-BF539/ADSP-BF539F ...
Page 56
... Y VDDRTC NC VROUTx Note: H18 and Y14 are NC for ADSP-BF539 and I/O (FCE and FRESET) for ADSP-BF539F Rev Page February 2008 lists the CSP_BGA ball assignment by ball Table 39 on Page 58 lists the CSP_BGA ball assign ...
Page 57
... R18 J8 GND M12 GND R19 J9 GND M13 GND R20 J10 GND M14 VDDINT T1 J11 GND M18 TFS3 T2 Rev Page February 2008 ADSP-BF539/ADSP-BF539F Ball No. Signal M19 ABE0 T3 GND M20 ABE1 T7 VDDEXT W2 N1 TFS0 T8 VDDEXT W3 DR0PRI T9 VDDEXT W4 GND T10 VDDEXT W5 VDDEXT T11 ...
Page 58
... ADSP-BF539/ADSP-BF539F Table 39. 316-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal ABE0 M19 DATA8 Y6 ABE1 M20 DATA9 W6 ADDR1 N19 DATA10 Y5 ADDR2 N20 DATA11 W5 ADDR3 P19 DATA12 Y4 ADDR4 P20 DATA13 W4 ADDR5 R19 DATA14 Y3 ADDR6 R20 DATA15 W3 ...
Page 59
... BSC BALL PITCH 0.12 MAX COPLANARITY 0.50 BALL DIAMETER 0.45 0.40 Rev Page February 2008 ADSP-BF539/ADSP-BF539F 15.20 BSC SQ A1 BALL BOTTOM VIEW 0.30 MIN SEATING PLANE DETAIL A ...
Page 60
... ADSP-BF539BBCZ-5A – + ADSP-BF539BBCZ-5F4 – + ADSP-BF539BBCZ-5F8 – + similar part is available for use in specific automotive applications. Contact your local ADI sales office for the ADBF539W Automotive Data Sheet which highlights any specification changes and ordering information. 2 Referenced temperature is ambient temperature ...