adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 38

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
Parallel Peripheral Interface Timing
Table 24
describe Parallel Peripheral Interface operations.
Table 24. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
PPI_FS1
PPI_FS2
PPI_DATA
POLS = 1
POLS = 0
POLS = 1
POLS = 0
and
Figure
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
19,
Figure
SCLK
20,
/2
1
Figure
21, and
t
HOFSPE
Figure 19. PPI GP Rx Mode with Internal Frame Sync Timing
FRAME
SYNC IS
DRIVEN
OUT
Figure 22
Rev. A | Page 38 of 60 | February 2008
t
DFSPE
t
SDRPE
DATA0
IS
SAMPLED
t
HDRPE
Min
6.0
15.0
5.0
1.0
2.0
4.0
0.0
0.0
Max
10.0
10.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns