adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 34

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adsp-bf539bbcz-5f8

Manufacturer Part Number
adsp-bf539bbcz-5f8
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
ADSP-BF539/ADSP-BF539F
Table 20. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
S = Number of programmed setup cycles, WA = Number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
DANR
HAA
DDAT
ENDAT
DO
HO
ADDR19–1
DATA15–0
CLKOUT
ABE1–0
AMSx
ARDY
AWE
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After ARE Negated
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
ENDAT
SETUP
t
t
DANW
DO
t
DO
Figure 15. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
BE, ADDRESS
WRITE DATA
PROGRAMMED WRITE
ACCESS 2 CYCLES
2
2
Rev. A | Page 34 of 60 | February 2008
1
EXTENDED
ACCESS
t
HO
1 CYCLE
HOLD
t
HAA
t
HO
Min
0.0
1.0
0.8
Max
(S+WA–2)
6.0
6.0
t
SCLK
Unit
ns
ns
ns
ns
ns
ns

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