adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 8

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
Table 3. System and Core Event Mapping (Continued)
Event Control
The ADSP-BF539/ADSP-BF539F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 16 bits wide:
Event Source
UART2 Error Interrupt
CAN Error Interrupt
Real-Time Clock Interrupt
DMA0 Interrupt (PPI)
DMA1 Interrupt (SPORT0 Rx)
DMA2 Interrupt (SPORT0 Tx)
DMA3 Interrupt (SPORT1 Rx)
DMA4 Interrupt (SPORT1 Tx)
DMA8 Interrupt (SPORT2 Rx)
DMA9 Interrupt (SPORT2 Tx)
DMA10 Interrupt (SPORT3 Rx)
DMA11 Interrupt (SPORT3 Tx)
DMA5 Interrupt (SPI0)
DMA14 Interrupt (SPI1)
DMA15 Interrupt (SPI2)
DMA6 Interrupt (UART0 Rx)
DMA7 Interrupt (UART0 Tx)
DMA16 Interrupt (UART1 Rx)
DMA17 Interrupt (UART1 Tx)
DMA18 Interrupt (UART2 Rx)
DMA19 Interrupt (UART2 Tx)
Timer0, Timer1, Timer2 Interrupts
TWI0 Interrupt
TWI1 Interrupt
CAN Receive Interrupt
CAN Transmit Interrupt
MXVR Status Interrupt
MXVR Control Message Interrupt
MXVR Asynchronous Packet Interrupt
Programmable Flags Interrupts
MDMA0 Stream 0 Interrupt
MDMA0 Stream 1 Interrupt
MDMA1 Stream 0 Interrupt
MDMA1 Stream 1 Interrupt
Software Watchdog Timer
• CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and is
Core
Event Name
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG13
IVG13
IVG13
IVG13
IVG13
Rev. A | Page 8 of 60 | February 2008
Each SIC allows further control of event processing by provid-
ing three 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
interrupt events shown in
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
• CEC Interrupt Pending Register (IPEND) – The IPEND
• SIC Interrupt Mask Registers (SIC_IMASKx)– These regis-
• SIC Interrupt Status Registers (SIC_ISRx) – As multiple
• SIC Interrupt Wake-up Enable Registers (SIC_IWRx) – By
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it can also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre-
sponding IMASK bit is cleared.
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
preventing the processor from servicing the event even
though the event can be latched in the ILAT register. This
register can be read or written while in supervisor mode.
(Note that general-purpose interrupts can be globally
enabled and disabled with the STI and CLI instructions,
respectively.)
register keeps track of all nested events. A set bit in the
IPEND register indicates whether the event is currently
active or nested at some level. This register is updated auto-
matically by the controller but can be read while in
supervisor mode.
ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servic-
ing the event.
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates that the
peripheral is asserting the interrupt, and a cleared bit indi-
cates that the peripheral is not asserting the event.
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled when the event is generated.
mation, see Dynamic Power Management on Page
Table 3 on Page
7.
(For more infor-
13.)