adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 5

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Internal (On-Chip) Memory
The ADSP-BF539/ADSP-BF539F processor has three blocks of
on-chip memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of 80K bytes
SRAM, of which 16K bytes can be configured as a four-way set-
associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32K bytes each. Each memory bank
is configurable, offering both cache and SRAM functionality.
This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratch pad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
DA1
DA0
LD1
LD0
SD
32
32
32
32
32
R1.H
R0.H
R7.H
R6.H
R3.H
R2.H
R5.H
R4.H
RAB
32
R0.L
R7.L
R2.L
R1.L
I3
I2
R6.L
R5.L
R4.L
R3.L
I1
I0
32
L3
L2
L1
L0
32
BARREL
SHIFTER
B3
B2
B1
B0
8
Rev. A | Page 5 of 60 | February 2008
32
ADDRESS ARITHMETIC UNIT
M3
Figure 2. Blackfin Processor Core
M2
M1
M0
A0
DATA ARITHMETIC UNIT
16
40
32
DAG1
8
40
40
The PC133-compliant SDRAM controller can be programmed
to interface to up to 512M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
Flash Memory (ADSP-BF539F Only)
The ADSP-BF539F4 and ADSP-BF539F8 processors contain a
separate flash die, connected to the EBIU bus, within the pack-
age of the ADSP-BF539F processors.
flash memory die and Blackfin processor die are connected.
8
DAG0
16
40
A1
ADSP-BF539/ADSP-BF539F
ASTAT
SP
P5
P3
P2
P1
P0
FP
P4
8
32
PREG
LOOP BUFFER
SEQUENCER
DECODE
CONTROL
ALIGN
Figure 4
UNIT
shows how the