adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 16

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
layout. The resistor value depends on the drive level specified by
the crystal manufacturer. System designs should verify the cus-
tomized values based on careful investigation on multiple
devices over the allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in
As shown in
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5× to 64× multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
CLKIN
CLKOUT
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure
REQUI RES PLL SEQUENCING
Figure
“FI NE” ADJUSTMENT
Figure 8. Frequency Modification Methods
0.5× TO 64×
Figure 7. External Crystal Connections
7.
PLL
EN
8, the core clock (CCLK) and system
CLKIN
18pF*
Blackfin
SCLK ≤ 133MHz
VCO
TO PLL CIRCUITRY
SCLK ≤ CCLK
XTAL
“COARSE” ADJUSTMENT
18pF*
÷ 1, 2, 4, 8
÷ 1:15
FOR OVERTONE
OPERATION ONLY
ON-THE-FLY
Rev. A | Page 16 of 60 | February 2008
CCLK
SCLK
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 7. Example System Clock Ratios
The maximum frequency of the system clock is f
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 8. Core Clock Ratios
BOOTING MODES
The ADSP-BF539/ADSP-BF539F processors have three mecha-
nisms (listed in
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
Table 9. Booting Modes
Signal Name
SSEL3–0
0001
0110
1010
Signal Name
CSEL1–0
00
01
10
11
BMODE1–0 Description
00
01
10
11
Table 7
8. This programmable core clock capability is useful for
illustrates typical system clock ratios.
Execute from 16-bit external memory
(bypass boot ROM)
Boot from 8-bit or 16-bit flash or boot from on-chip
flash (ADSP-BF539F only)
Boot from SPI serial master connected to SPI0
Boot from SPI serial slave EEPROM /flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)
connected to SPI0
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Table
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
9) for automatically loading internal L1
SCLK
Example Frequency Ratios (MHz)
VCO
100
300
500
. The SSEL value can be changed
Example Frequency Ratios
VCO
300
300
500
200
SCLK
100
50
50
CCLK
300
150
125
25
SCLK
. Note that