mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 19

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

MCU read cycle access time is used to determine the number of wait states needed for a given memory
speed, because it is longer than write cycle access time, and is thus the limiting factor.
As an example, the equations below are solved for zero wait states, assuming 16.78 MHz timing:
The equations can also be solved for the number of wait states needed, given the memory speed. Use Ta-
ble 3 to find the number of wait states required for a particular memory speed. For example, with a 16.78
MHz clock, a memory with a write cycle time of 130 ns requires one wait state, since 130 ns is between 89.2
ns and 148.8 ns.
2.9.2 Using Chip-Select Signals to Enable Boot Memory
The MCU CSBOOT chip-select circuit is always enabled from reset. Because the internal SRAM module is
disabled out of reset, the CSBOOT signal is generally used to select an external boot ROM. The CSBOOT
chip-select circuit features hardware-controlled selection of 8-bit or 16-bit bus width. Bus width is controlled
MC68331/332
M68331/332TUT/D
Clock Period (t
Clock Low to AS, DS, CS Asserted (t
Data In Valid to Clock Low (Data Setup) (t
Clock High to Address, FC, SIZE, RMC Valid (t
Clock Low to AS, DS, CS Negated (t
States
Wait
F.T.
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Address access time = 2.5 X 59.6 ns – 29 ns – 5 ns = 115 ns
Chip-select access time (MCU read cycle) = 2 X 59.6 ns – 25 ns – 5 ns = 89.2 ns
Chip-select access time (MCU write cycle) = 2 X 59.6 ns – 25 ns + 2 ns = 96.2 ns
Memory Write Access
CS Read Access/
CYC
148.8
208.4
268.0
327.6
387.2
446.8
506.4
566.0
625.6
685.2
744.8
804.4
864.0
Table 2 Parameters Needed for Calculating Memory Access Times
)
29.6
89.2
Parameter
16.78 MHz
Table 3 Memory Access Times in Nanoseconds
Freescale Semiconductor, Inc.
For More Information On This Product,
Address
Access
115.0
174.6
234.2
293.8
353.4
472.6
532.2
591.8
651.4
770.6
830.2
889.8
CLSN
55.4
CLSA
413
711
)
)
DICL
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Memory Write Access
CHAV
)
CS Read Access/
)
59.6 ns
115.1
162.8
210.5
258.2
305.9
353.6
401.3
449.0
496.7
544.4
592.1
639.8
687.5
19.7
67.4
2 ns
5 ns
2 ns
Min
0
20.97 MHz
16.78 MHz
25 ns
29 ns
29 ns
Max
—
—
Address
Access
138.95
186.65
234.35
282.05
329.75
377.45
425.15
472.85
520.55
568.25
615.95
663.65
711.35
43.55
91.25
47.7 ns
5 ns
2 ns
Min
0
0
20.97 MHz
Memory Write Access
CS Read Access/
23 ns
23 ns
23 ns
Max
—
—
134.8
174.5
214.2
253.9
293.6
333.3
373.0
412.7
452.4
492.1
531.8
571.5
15.7
55.4
95.1
25.17 MHz
39.7 ns
5 ns
2 ns
Min
2
0
25.17 MHz
Address
Access
114.95
154.65
194.35
234.05
273.75
313.45
353.15
392.85
432.55
472.25
511.95
551.65
591.35
19 ns
35.55
75.25
19 ns
19 ns
Max
—
—
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