mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 46

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

To clear an interrupt, negate the appropriate interrupt status flag in the channel interrupt status register
(CISR). Read the flag in the asserted state and then write a zero to the bit. As long as the CISR bit is set,
the channel will continue to request interrupts.
4.6.4 TPU Initialization Examples
The following example initializes channel zero to run the PWM function. The output of channel zero will be
a 50% duty cycle square wave. The frequency will be (SYSCLK/4)/$4000. For 16.778 MHz, this is
(4194500/16384) = 256 Hz. It assumes that the “MM” bit in the SIMCR is set to one. The PWM function
generates an interrupt on each rising edge. The interrupt routine increments data register D0 at each inter-
rupt.
This example is in the file “tpuinit.asm” in the archive “331_2ini.zip” on the Freeware Data System. It can be
assembled with the IASM32 assembler.
46
2. Store an interrupt priority level for the TPU in bits ten through eight of the TICR.
3. Store an interrupt arbitration value in the IARB field of the TPU module configuration register.
4. Set the interrupt enable bit for the channel in the channel interrupt enable register (CIER). This sim-
The location in the vector table where the service routine starting address is stored is called the vector
address. The vector address is calculated from the interrupt vector number — it is four times the vec-
tor number plus the value in the vector base register.
The interrupt vector number is formed by concatenating a base vector number with the channel num-
ber. Choose a base vector number and write it to bits seven through four in the TPU interrupt config-
uration register (TICR). For example, choosing a base vector number of $80 would assign interrupt
vector $80 to channel zero, interrupt vector $81 to channel one, interrupt vector $82 to Channel two,
and so on, through assignment of interrupt vector $8F to channel 15.
For example, if channel four is being set up to request interrupt service, the interrupt vector is $84.
Assuming the vector base register holds a value of zero, the vector address is:
4 $84
Thus, the starting address of the interrupt routine must be stored in location $210.
This value determines the priority of TPU interrupt service requests. The value must be a number be-
tween one and seven — level seven has the highest priority, and level one has the lowest. The value
stored in the IPL field in the CPU status register determines whether an interrupt request is recog-
nized. The value in the IPL field must be lower than the TPU interrupt priority level in order for the
TPU to interrupt the CPU, unless the interrupt level is seven, in which case it cannot be masked.
The IARB field value determines precedence when the CPU receives more than one interrupt request
of the same interrupt priority level. Each interrupting module must be assigned a unique IARB number
between $01 (lowest precedence) and $0F (highest precedence).
ply involves writing the channel's bit number to a one.
#SIZING_ON
INITSYS:
CNTLREG:
$00
INCLUDE
INCLUDE
INCLUDE
ORG
CLR.L
MOVEC
MOVE.B
CLR.B
MOVE.W
$210
Freescale Semiconductor, Inc.
For More Information On This Product,
'equ332.asm'
'init_res.asm'
'init_int.asm'
$400
D0
D0,VBR
#$7F,SYNCR
SYPCR
#$0009,CFSR3
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;include equates
;include reset vector
;include interrupt vectors
;begin program at $400, immediately after
;the exception table
;make sure that VBR is initialized to zero
;it is initialized to 0 out of reset
;set system clock to 16.78 MHz
;disable software watchdog
;channel function select field. Note:
M68331/332TUT/D
MC68331/332