mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 40

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

4.4.3 Initializing QSM Interrupts
To enable interrupts on the QSM, initialize the following five fields:
4.5 Configuring the General-Purpose Timer
The general-purpose timer (GPT) is a module on the MC68331. The MC68332 does not have a GPT. The
GPT is a software-interrupt driven timer that is very similar to the timer used extensively on the M68HC11
series of microcontrollers. Because the GPT uses design rules for the M68300 family, the GPT runs four
times faster on the M68300/M68HC16 families than it does on the M68HC11 family. While the GPT does
reside on the intermodule bus, it does not have a self-contained arithmetic logic unit or RISC-like mi-
croengine (like the time processor unit on other modular MCUs) with specialized instruction sets. The GPT
functions are briefly described below. For a more detailed explanation, refer to the GPT Reference Manual
(GPTRM/AD).
Input Capture Pins (IC1-IC3): Each of these pins is associated with a single input capture function and has
a dedicated 16-bit capture register to hold the captured counter value. These pins can also be configured
for general-purpose I/O.
Output Compare Pins (OC1-OC4): Each of these pins has a dedicated 16-bit compare register and 16-bit
comparator. Pins OC2, OC3, and OC4 are associated with a specific output compare function, whereas,
the OC1 function can affect the output of any combination of output compare pins. Automatic prepro-
grammed pin actions occur on a successful match. The OC1 pin can alternately be used to output the clock
selected for the timer counter register (TCNT). Also, any of the pins can be used for general-purpose I/O.
Pulse Accumulator Input Pin (PAI): The pulse accumulator counter (PACNT) is an 8-bit read/write up-
counter register that can operate in an external event counting or gated time accumulation mode. The user
software can write the number of edges to be counted to the PACNT register. As the edges are counted,
the counter will approach $FF, roll over to $00, and generate an interrupt. The pulse accumulator overflow
flag will indicate that the count has rolled over.
Pulse-Width Modulation (PWMA, PWMB): These are the outputs to the two PWM functions. They can be
programmed to generate a periodic waveform with a variable frequency and duty cycle. Alternately, these
pins can be used for general-purpose I/O. PWMA can also be used to output the clock selected as the input
to the PWM counter (PWMCNT).
Auxiliary Timer Clock Input (PCLK): This is an external clock input dedicated to the GPT that can be used
as the clock source for the capture/compare unit or the PWM unit in place of one of the prescaler outputs.
If this pin is not used as a clock input, it can be used as a general-purpose input pin.
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1. ILPQSPI and ILSCI in the QILR register determine the priority levels of QSPI and SCI interrupts, re-
2. INTV[7:0] in the QIVR register determines the interrupt vector number. For the QSPI, the least sig-
3. IARB in the QSMCR register determines precedence if the QSM and another module simultaneously
4. IPL in the CPU status register determines the priority level at which interrupts are recognized. In order
5. The interrupt vector tells the processor where to find the interrupt service routine. Store the starting
spectively. If the fields are set to the same level, the QSPI takes priority.
nificant bit is read as a one, and for the SCI, the least significant bit is read as a zero.
make an interrupt service request of the same priority. This field must be initialized to a unique, non-
zero value if interrupts are enabled.
for QSM interrupts to be recognized, this field must be given a value that is lower than the interrupt
priority level specified in the QILR register.
address of the service routine in the interrupt vector table at the appropriate vector offset address.
The vector offset address is equal to (interrupt vector number X 4) + address stored in the VBR.
INT
DATA
RTE
DB 16
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;unused interrupts point here
;Set aside memory space for the data to be
;transmitted. This program does not
;initialize the data.
M68331/332TUT/D
MC68331/332