mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 23

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

2.10.3 Interrupt Vectors
Vectors are 32-bit addresses that point to the interrupt service routines (and other exception handlers). They
are stored in a data structure called the exception vector table. There are 256 vector addresses in the ex-
ception vector table; of these, 199 can be used for interrupts. The base address of the exception vector table
is determined by the value stored in the vector base register. A vector number is used to calculate the vector
address, i.e., a displacement into the exception vector table.
2.10.4 The Interrupt Acknowledge Cycle
After the CPU recognizes a valid interrupt request, the CPU begins the interrupt acknowledge (IACK) cycle.
The CPU changes the IPL mask value to the level of the acknowledged interrupt to preclude lower-or-equal
priority interrupt requests, then initiates a read cycle in CPU space. Since there is no dedicated IACK pin
on the MCU, an external IACK signal is usually provided by a chip-select pin.
Vector numbers can be supplied by the device requesting interrupt service, or they can be generated auto-
matically. Vector numbers supplied by the device cause the CPU to access one of 192 user vectors in the
exception vector table; automatically generated vectors cause the CPU to access one of the seven autovec-
tors in the table. Each method of vector number acquisition requires a different form of IACK cycle termina-
tion. If a vector number is supplied, either the requesting device must terminate the IACK cycle with a
DSACK signal or the chip-select logic must generate the DSACK signal internally. If an autovector is used,
an external device can assert the AVEC signal or an AVEC signal can be generated by the chip-select logic.
Since normal bus cycles occur in user or supervisor space, but an IACK cycle occurs in CPU space, the
same chip-select circuit cannot be used to terminate both an IACK cycle and a normal bus cycle.
2.10.4.1 User Vectors
Once an interrupting device has placed a user vector number on the external data bus in response to an
IACK signal from the MCU, either the device must terminate the IACK cycle with DSACK, or the chip-select
logic must generate DSACK internally. When the bus cycle has been terminated, the vector number is left-
shifted twice (multiplied by four), then a 32-bit vector address is formed by concatenating the upper 22 bits
of the vector base register, the shifted value, and %00. The CPU then saves the current context, loads the
32-bit vector into the PC, and begins to execute the service routine at that address.
An example is shown in Figure 16. Chip select one is configured for interrupt acknowledge and automatic
generation of the DSACK signal. It is connected to the IACK pin of the peripheral. Because the processor
drives $FFFFFx onto the address bus and drives the function code pins to indicate CPU space during an
IACK cycle, the chip-select base address register must be programmed to $FFFX. When the CPU recog-
nizes an interrupt and initiates an IACK cycle, CS1 is asserted. In response, the peripheral drives an 8-bit
vector number onto the data bus. Chip-select logic then terminates the IACK cycle with DSACK.
MC68331/332
M68331/332TUT/D
Figure 16 Chip-Select Line Used for Interrupt Acknowledge
Freescale Semiconductor, Inc.
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MC68332
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CS0
CS1
D15
D14
D13
D12
D10
D11
D9
D8
PERIPHERAL
CS
IACK
D7
D6
D5
D4
D3
D2
D1
D0
332TUT PERI CONN
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