mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 45

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

conflicts do not occur within the host service request registers. If the channels are running, and cannot be
disabled, write the host service request field for the first channel, then poll those bits until the TPU clears
them. Then, write the host service request field for the second channel, wait until the TPU clears it, and so
on.
4.6.1.5 Channel Priority Registers
The channel priority registers determine how often each channel is serviced. There are three priority levels:
high, medium, and low. If the priority bits are set to zero, then a channel is disabled, and the TPU mi-
croengine will not service it.
4.6.2 Parameter RAM Registers
Each channel has a dedicated set of word-long registers (called parameters) in the parameter RAM. TPU
channels zero–13 have five parameters, and channels 14 and 15 have seven parameters. The CPU and
the TPU communicate through the parameter RAM. The meaning of each location in the parameter RAM is
defined by the microcode for a particular function. All writes to the TPU parameter RAM registers must be
word-length operations. If a byte write is attempted, the value $FF will be written to the other half of the reg-
ister.
In the TPU manual, addresses in parameter RAM for channels zero to 13 are defined as $YFFFW0,
$YFFFW2, $YFFFW6, $YFFFW8, and $YFFFWA. Channels 14 and 15 have the additional parameters
$YFFFWC and $YFFFWE. The “Y” is either an F or a seven, depending on the “MM” bit in the SIM module
configuration register. Out of reset, the “Y” is an F. The “W” is the channel number. The last number is the
location of the channel parameters. For example, out of reset, the first parameter for TPU channel 10 is lo-
cated at $FFFFA0.
TPULITPAK/D contains programming notes for all the A and G mask functions. See the programming note
that pertains to a particular function for a parameter diagram, field encodings, and a description of the op-
tions that are available.
4.6.2.1 The Channel Control Register
The channel control register (CCR) is a parameter that is common to most functions. It is nine bits long, and
it is usually the first parameter. The CCR allows the CPU to pass information concerning channel configu-
ration to the TPU. The microcode for a particular function determines the meaning of data in the CCR. The
function may or may not use all of the information, because the microcode can configure the channel without
help from the CPU. Usually, the TPU overwrites the CCR after initialization and uses the space for a TPU-
controlled parameter.
In general, the channel control register consists of three fields:
See the programming note that pertains to a particular function for specific information about the channel
control field.
4.6.3 TPU Interrupts
Several steps must be followed in order for a TPU channel to request interrupt service.
MC68331/332
M68331/332TUT/D
1. The time base select (TBS) field determines which timer count register (TCR) the channel uses. The
2. The pin action control (PAC) field has two basic functions. For an output channel, the PAC field de-
3. The pin state control (PSC) field determines initial pin state immediately after a host service request.
1. Store the starting address of the interrupt service routine in the CPU interrupt vector table.
channel can match and capture TCR1 and TCR2. The TPU is also capable of matching one TCR and
capturing the other.
termines what type of transition the pin will make when a match occurs. For an input channel, the
PAC field determines what type of transition the pin will detect.
Freescale Semiconductor, Inc.
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