mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 50

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

5.2.5 Problem: Debug System Cannot Enter BDM
5.2.6 Problem: The Processor Takes a Spurious Interrupt Exception
An interrupt request signal must remain asserted from the time it first occurs until the end of the IACK cycle.
The most common cause of spurious interrupts is a periodic signal, such as a square wave, connected to
an external interrupt request line. Other signals, such as the output of a shaft decoder, will also cause spu-
rious interrupts. Latch periodic or intermittent signals by means of an external circuit, and clear the latch in
the interrupt service routine.
5.2.7 Problem: The Processor Asserts HALT and Halts
A double bus fault has occurred, and the halt monitor (previously called the double bus fault monitor) is not
enabled. A double bus fault can occur under the following conditions.
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1. BKPT is not held low at the release of RESET. Holding BKPT low at the release of RESET enables
2. The memory is uninitialized, and the processor is trying to access bad addresses. In this case, most
1. The interrupt arbitration (IARB) field for the module requesting interrupt service is not a unique, non-
2. There are noise spikes on an IRQ line. Use pull-up resistors on the IRQ lines.
3. A square wave is used to generate external interrupts, and the source of the interrupt is going away
4. The program code is disabling an internal module or is using the BCLR instruction to arbitrarily clear
5. An internal module is initialized improperly in such a way that the module cannot respond with an
6. The IACK cycle is terminated by BERR instead of DSACK or AVEC. The assertion of BERR causes
1. When bus error exception processing begins, and a second bus error is detected before the first in-
2. When one or more bus errors occur before the first instruction after a reset is executed.
happens, the driven pins on the device with the slow supply will momentarily have a higher voltage
than the V
ward biased and cause significant current injection into the device substrate, which will probably im-
properly charge or discharge some of the internal nodes of the MCU. This action is completely
random, and it is impossible to predict what will happen when significant injection occurs. Usually,
the MCU will not function at all and will display undefined states. For example, the RESET, HALT,
BERR, BR and FREEZE signals may be asserted but the device may fail to fetch opcodes. See 2.7
Power Supply.
BDM, and driving it low after reset causes the processor to enter BDM. The debugger should take
care of this.
debuggers should drive BERR to terminate the bus cycle. If the debugger does not do this, either
write valid addresses to the reset vectors or, if this is not possible, manually pulse BERR low to ter-
minate a hung bus cycle.
zero value. Each internal module has its own IARB field. External interrupts use the IARB field in the
SIMCR interrupts.
before the interrupt is acknowledged.
interrupt enable bits for an internal module before the interrupt is acknowledged. Instead of arbitrarily
clearing the enable bits, first mask out the interrupt level by writing to the IPL field in the CPU status
register. For example, if a level three interrupt is to be masked, set the IPL field to three or higher.
Then, disable the enable bit for the specific interrupt.
internal DSACK even when that module is the one asserting the interrupt.
the spurious interrupt vector (vector number 24) to be taken. A spurious interrupt will be taken in the
following three situations:
A. The CPU recognizes the occurrence of a valid interrupt request and begins the IACK cycle. If none
B. After arbitration, the interrupt source that wins arbitration does not terminate the IACK cycle with
C. An external device terminates the IACK cycle by asserting BERR.
struction of the first exception handler is executed.
of the modules enter arbitration by asserting an IARB field value, the spurious interrupt monitor
asserts BERR internally.
DSACK or AVEC. In this case, the bus monitor asserts the internal BERR signal.
DD
pin. This condition can cause the input protection diodes to become momentarily for-
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M68331/332TUT/D
MC68331/332