pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 109

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

3.10
The framer interface of the QuadLIU
Figure 42
Configuring of the framer interface consists on
•
•
Selection of dual or single rail mode can be done in receive and transmit direction independent from each other.
In single rail mode of the receive direction (LIM3.DRR = ´0´, LIM3), the unipolar data is supported at RDOP and
the bipolar violation (BPV) is supported at the receive multifunction pins. Therefore one of the three receive
multifunction pins must be configured to RDON/BPV output (for example PC3.RPX3(3:0) = ´1110
if BPV output is used exernally.
If dual rail mode is selected in receive direction by setting of register bit LIM3.DRR, the positive rail of the data is
supported at RDOP and the negative rail of the data or is supported at the receive multi function pins. Therefore
one of the three receive multifunction pins must be configured to RDON/BPV output,
Clocking of RDOP and RDON/BPV is done with the rising or falling edge of the internal receive clock, selected by
DIC3.RESR. The internal receive clock can be sourced either
•
Data Sheet
Configuration of the interface mode (single/dual rail)
Configuration of the multi function ports, see
By the receive clock RCLK of the receive system (CMR2.IRSC = ´1´, CMR2). To support the framer with these
clock FCLKR output pin function must be selected by PC5.CSRP = ´1´ (PC5). or
Framer Interface
Framer Interface (shown for one channel)
DCO-R
from
(see chapter 3.8.)
(see chapter 3.6)
Transmit System
Receive System
Dual Transmit
Dual Receive
Elastic Buffer
Eastic Buffer
recovered
clock
J: controlled by CMR2.IRSC and DIC1.RBS(1:0)
K: controlled by CMR2.IXSC
1: Input/output selection of FCLKR by PC5.CSRP
J
TM
internal
receive clock
RDOP
RDON/BPV
LOS
RCLK
FCLKX
internal
transmit
clock
TCLK
XDIN
XDIP
is shown in
Chapter 3.12
Figure
Transmit
Interface
Interface
Receive
109
Framer
Framer
K
42.
RDON/BPV
LOS
RCLK
XDIN
TCLK
XCLK
Multi Function
Multi Function
Ports
Ports
QLIU_framer_if
1
seeTable
Functional Description
FCLKR
FCLKX
XP(A...B)
XDIP
RDOP
RP(A...C)
Rev. 1.3, 2006-01-25
34.
b
´),
QuadLIU
PEF 22504
seeTable
34,
TM