pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 81
pef22504
Manufacturer Part Number
pef22504
Description
Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF22504.pdf
(255 pages)
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Table 13
Line Code,
Framer IF
Mode
3.6.1
If the register bit BFR.BPV is set to ´0´ and after execution of the sequence described below, Bipolar Violations
(BPV) consisting on single ´1´ pulses (separated from the previous ´1´ pulse by at least one ´0´ pulse) or on two
consecutive ´1´ pulses are detected correctly and thus counted by the bipolar violation counter. Bipolar Violations
(BPV) consisting on more than two consecutive ´1´ pulses are not detected correctly and thus not counted by the
bipolar violation counter.
Compatibel to the QuadFALC V2.1, Bipolar Violations (BPV) are not detected correctly and thus not counted by
the bipolar violation counter, if BFR.BPV is set to ´1´ (default after reset).
If the second of two consecutively received Alternate Mark Inversion (AMI) pulses is a BPV (second pulse has the
same polarity as the first pulse) and BFR.BPV is set to ´1´, the receiver converts the second AMI pulse to a logic
zero. This conversion will cause a bit error and will mask detection and counting of the BPV. In contrast, any BPV
separated from the previous ´1´ pulse by at least one ´0´ pulse is detected, counted, and recorded correctly
This BPV conversion is not expected to cause any system level problems. BPV counts, bit errors counts, and CRC
counts may be slightly inaccurate, depending on the BPV rate. Note that the special B8ZS and HDB3 substitution
do not contain consecutive BPV pulses so the conversion described above will not occur when receiving these
patterns
The behaviour of the Bipolar Violation Detection is illustrated in
Data Sheet
Line Coding and Framer Interface Modes (cont’d)
Bipolar Violation Detection
Register Bits
FMR0.RC,
LIM3.DRR
0 -> 1 or 1
-> 0
FMR0.XC,
LIM3.DRX
Asynchron
(Motorola
or Intel)
SPI or SCI If pinstrap
Signals at Pins
RDON (RPC)
If actual values
of N or M in
GCM5 or GCM6
are different to
internal settings
of the “clocking
fixed mode”
values are
different to
internal settings
of the “clocking
fixed mode”;
That is not
allowed!
81
RDO
Figure
21.
XDI
Functional Description
Rev. 1.3, 2006-01-25
XDIN (XPB)
QuadLIU
PEF 22504
TM
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