pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 63
pef22504
Manufacturer Part Number
pef22504
Description
Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF22504.pdf
(255 pages)
- Current page: 63 of 255
- Download datasheet (8Mb)
Table 2
Pin No.
45
64
117
136
1
36
73
108
11
56
102
125
135
Power Supply Configuration
134
Boundary Scan/Joint Test Access Group (JTAG)
131
112
141
140
Data Sheet
113
Name
V
V
TRS
TDI
TMS
TCK
TDO
SS
SEL
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
S
I + PU
I
O
Buffer
Type
–
–
PD
PU
–
Function
Power Ground
Common for all sub circuits (0 V)
For correct operation, all V
ground.
Voltage Select
Enables the internal voltage regulator for 3.3 V only operation
mode if connected to V
Disables the internal voltage regulator for dual power supply
mode (1.8 V and 3.3 V) if connected to V
Test Reset
For Boundary Scan (active low). If not connected, an internal
pulldown transistor ensures low input level.
Test Data Input
For Boundary Scan.
If not connected an internal pullup transistor ensures high
input level.
Test Mode Select
For Boundary Scan.
If not connected an internal pullup transistor ensures high
input level.
Test Clock
For Boundary Scan.
If not connected an internal pullup transistor ensures high
input level.
Test Data Output
For Boundary Scan
63
DD
(recommended) or left open.
SS
pins have to be connected to
Rev. 1.3, 2006-01-25
SS
Pin Descriptions
.
QuadLIU
PEF 22504
TM
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