pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 68

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

In the Intel mode write access READY will be set to low by the QuadLIU
driven by the micro controller). After WR is high and data are written successfully into the registers of the
QuadLIU
The general timing diagrams are shown in
The communication between the external micro controller and the QuadLIU
accessible registers. The interface can be configured as Intel or Motorola type with a selectable data bus width of
8 or 16 bits.
The external micro controller transfers data to and from the QuadLIU
function sequences, and gets status information by writing or reading control and status registers. All accesses
can be done as byte or word accesses if enabled. If 16-bit bus width is selected, access to lower/upper part of the
data bus is determined by address line A0 and signal BHE / BLE as shown in
Table 6
The switching of ALE allows the QuadLIU
3.5.1.1
Reading from or writing to the internal registers can be done using a 8-bit (byte) or 16-bit (word) access depending
on the selected bus interface mode. Randomly mixed byte/word access is allowed without any restrictions.
Table 4
BHE
0
0
1
1
Table 5
BLE
0
0
1
1
Table 6
ALE
Constant
level
Switching
The assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends
on the selected asynchronous microprocessor interface mode:
Data Sheet
shows how the ALE (Address Latch Enable) line is used to control the bus structure and interface type.
TM
A0
0
1
0
1
, READY will be set to high by the QuadLIU
A0
0
1
0
1
Mixed Byte/Word Access
Data Bus Access (16-Bit Intel Mode)
Data Bus Access (16-Bit Motorola Mode)
Selectable asynchronous Bus and Microprocessor Interface Configuration
IM(1:0) Asynchronous Microprocessor Interface Mode Bus Structure
01
00
00
Register Access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
Register Access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
Motorola
Intel
Intel
TM
Figure 51
to be directly connected to a multiplexed address/data bus.
to
TM
68
Figure
.
56.
TM
TM
, sets the operating modes, controls
after the falling edge of WR (which is
De-multiplexed
De-multiplexed
Multiplexed
QuadLIU
D(15:0)
D(15:8)
D(7:0)
None
QuadLIU
D(15:0)
D(7:0)
D(15:8)
None
Table 4
TM
is done using a set of directly
TM
TM
and
Functional Description
Data Pins Used
Data Pins Used
Table
Rev. 1.3, 2006-01-25
5.
QuadLIU
PEF 22504
TM