pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 157

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Field
IRSP
IRSC
IXSC
Data Sheet
Bits
3
2
0
Type
rw
rw
rw
Description
Internal Receive System Frame Sync Pulse
Note: Recommendation: This bit should be set to ´1´.
0
1
Internal Receive Digital (Framer) Clock
0
1
Internal Transmit Digital (Framer) Clock
0
1
B
B
B
B
B
B
(free running).
sourced by the DCO-R circuitry. This internally generated frame
sync signal can be output (active low) on multifunction ports RP(A
to D) (RPC(3:0) = ´0001
FCLKR or in receive elastic buffer bypass mode from the
corresponding extracted receive clock RCLK.
internally by DCO-R or in bypass mode by the extracted receive
clock. FCLKR is ignored.
FCLKX.
internally by the working clock of the receive framer interface.
FCLKX is ignored.
The frame sync pulse is derived from RDOP output signal internally
The frame sync pulse for the receive system interface is internally
The working clock for the receive framer interface is sourced by
The working clock for the receive framer interface is sourced
The working clock for the transmit framer interface is sourced by
The working clock for the transmit framer interface is sourced
157
Register DescriptionClock Mode Register 2
H
´).
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM